PDF CXP912032 Data sheet ( Hoja de datos )

Número de pieza	CXP912032
Descripción	CMOS 16-bit Single Chip Microcomputer
Fabricantes	Sony Corporation
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No Preview Available ! CXP912032 CMOS 16-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP912032 is a CMOS 16-bit micro-computer integrating on a single chip an A/D converter, serial interface with an incorporated buffer RAM, high- precision timing pattern generation function, pulse cycle measurement circuit, PWM generator, general- purpose prescaler, vertical sync separation circuit, and a measurement circuit which measures the signals of capstan FG, drum FG/PG, reel FG and other servo systems with high precision, as well as basic configurations like a 16-bit CPU, ROM, RAM, and I/O port. This LSI also provides sleep/stop modes that enable lower power consumption. 100 pin QFP (Plastic) 100 pin LQFP (Plastic) 104 pin LFBGA (Plastic) Features • An efficient instruction set as a controller — Direct addressing, numerous abbreviated forms, multiplication and division instructions • Instruction sets for C language and RTOS — Highly quadratic instruction system, general-purpose register of 16-bit × 8-pin × 16-bank configuration • Minimum instruction cycle time operation 100ns at 20MHz Structure • Incorporated ROM capacity 128K bytes Silicon gate CMOS IC • Incorporated RAM capacity 6144 bytes • Peripheral functions — A/D converter 8-bit 12-channel successive approximation system, automatic scanning function, 8-stage (soft) + 4-stage (hard) FIFO for conversion results (Conversion time: 20µs at 20MHz) — Serial interface Buffer RAM (128 bytes, supports high-speed transfer mode), 3 channels — Timers 8-bit timer/counter + 8-bit timer (with timing output), 1 channel 16-bit capture timer/counter (with timing output), 1 channel 16-bit timer, 4 channels — High-precision timing pattern generator PPG for 27 pins, 42 stages (max.) PPG for 16 pins, 16 stages (max.) RTG for 5 pins, 3 channels — PWM/DA gate output PWM for 14 bits, 2 channels (Repetitive frequency of 39.1kHz, 20MHz) DA gate pulse for 14 bits, 2 channels — Servo input control Capstan FG, drum FG/PG, reel FG — VSYNC separator — FRC capture unit 24-bit and 8-stage FIFO — PWM output 14 bits, 2 channels — General-purpose prescaler 10 bits, 1 channel — Pulse cycle measurement circuit 1 channel with mask input • General-purpose I/O 80 pins (max.; when all multi-purpose pins are used as general-purpose I/O.) • Interruption 28 factors, 28 vectors, multi-interruption and priority selection possible • Standby mode Sleep/stop • Package 100-pin plastic QFP/LQFP, 104-pin plastic LFBGA • Piggyback/evaluation chip CXP912000 100-pin ceramic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95Y30B86-PS 1 page Pin Configuration 3 (Top View) 104-pin LFBGA Package CXP912032 1 2 3 4 5 6 7 8 9 10 11 12 13 A A1 NC A3 A4 A5 A6 A7 A8 A9 A10 A11 PB1 PA7 PA4 PA1 VSS NC PJ5 PJ2 PJ0 A13 NC B B3 B4 B5 B6 B7 B8 B9 B10 B11 PB2 PB0 PA5 PA2 VDD PJ7 PJ4 PJ1 AVDD C C1 C2 PB6 PB5 C4 C5 C6 C7 C8 C9 C10 PB3 PA6 PA3 PA0 PJ6 PJ3 AVREF C12 C13 AN3 AN2 D D1 D2 D3 PC0 PB7 PB4 D11 D12 AVSS AN1 D13 PI7 E E1 E2 E3 PC3 PC2 PC1 E11 VSS E12 PI6 E13 PI5 F F1 F2 F3 PC6 PC5 PC4 F11 F12 PI4 PI3 F13 PI2 G G1 G2 G3 VSS PC7 PD0 G11 G12 G13 PI1 SCK0 PI0 H H1 H2 H3 PD1 PD2 PD3 H11 H12 H13 CS0 SI0 SO0 J J1 J2 J3 PD4 PD5 PD6 J11 J12 J13 PH5 PH6 PH7 K K1 K2 K3 PD7 PE0 PE3 K11 K12 K13 PH0 PH3 PH4 L L1 L2 PE1 PE2 L4 L5 L6 L7 L8 L9 L10 PE4 PF1 PF4 VSS VDD PG2 PG7 L12 L13 PH1 PH2 M M3 M4 M5 M6 M7 M8 M9 M10 M11 PE5 PE7 PF2 PF5 PF7 EXTAL PG1 PG4 PG6 N N1 NC N3 PE6 N4 PF0 N5 PF3 N6 N7 N8 N9 N10 PF6 RST XTAL PG0 PG3 N11 PG5 N13 NC Note) 1. Vss (Pins A7, E11, G1 and L7) must be connected to GND. 2. VDD (Pins B7 and L8) must be connected to VDD. 3. NC (Pins A1, A13, N1, N13 and A8) are left open. 4. A1, A13, N1 and N13 pins are reinforced balls. –5– 5 Page CXP912032 Pin Circuit format Port F "0" after a reset Port F function selection After a reset PF5/SCK1 Internal serial clock from SIO Port F data MPX Hi-Z 1 pin Data bus RD (Port F) Hi-Z control SIO Schmitt trigger input Port F "0" after a reset Port F function selection IP PF6/T1 PF7/T2 Timer/counter "1" when reset Port F data MPX "H" level 2 pins Data bus RD (Port F) PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/DA0 PG5/DA1 Port G "0" after a reset Port G function selection DA gate output or PWM output Port G data MPX Hi-Z 6 pins PG6/RFG0 PG7/RFG1 2 pins PH0/EXI0 PH1/EXI1 PH2/SYNC0/PMI PH3/SYNC1 PH4/PMSK PH5/DPG PH6/DFG PH7/CFG 8 pins Port G Data bus RD (Port G) Schmitt trigger input Hi-Z control IP Servo circuit Data bus Port H RD (Port G) Schmitt trigger input IP Servo circuit Data bus RD (Port H) Note) PH2/SYNC0/PMI and PH3/SYNC1 can select CMOS Schmitt trigger input or TTL Schmitt trigger input with the mask option. Hi-Z Hi-Z – 11 – 11 Page

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