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PDF LP3950 Data sheet ( Hoja de datos )
| Número de pieza | LP3950 | |
| Descripción | Color LED Driver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LP3950 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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February 2005
www.DataSheet4U.com
LP3950
Color LED Driver with Audio Synchronizer
General Description
The LP3950 is a color LED driver with a built-in audio
synchronization feature for any analog audio input such as
polyphonic ring tones and MP3 music. LEDs can be syn-
chronized to an audio signal with two methods - amplitude
and frequency. Also several fine tuning options are available
for differentiation purposes. The chip also has an unique
AGC (Automatic Gain Control) feature which tracks the input
signal level and automatically adjusts the gain to an optimal
value.
The LP3950 has a high efficiency magnetic DC/DC con-
verter with programmable output voltage and switching fre-
quency. The converter has high output current capability so it
is also able to drive flash LEDs in camera phone applica-
tions.
The LP3950 is similar to LP3933 and LP3936 in that the
color LEDs (or RGB LEDs) can also be programmed to
generate light patterns (programmable color, intensity, on/off
timing, slope and blinking cycle).
All functions are software controllable through a SPI or I2C
compatible interface but the device also supports one pin
control for enabling predefined (default) audio synchroniza-
tion mode.
Features
n Audio synchronization for color LEDs with two modes:
Amplitude and Frequency
n Programmable frequency and amplitude response with
tracking speed control
n Automatic gain control or selectable gain for input signal
optimization
n RGB pattern generator similar to LP3933/LP3936
n Magnetic DC-DC boost converter with programmable
boost output voltage
n Selectable SPI or I2C compatible interface
n One pin default enable for non-serial interface users.
One pin selector for synchronization mode
n Space efficient 32-pin thin CSP laminate package
Applications
n Cellular phones
n MP3/CD/minidisc players
n Toys
Typical Application
© 2005 National Semiconductor Corporation DS201293
20129301
www.national.com
1 page  
Electrical Characteristics (Notes 2, 11) (Continued)
Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperawturwe wma.Dy ahataveShtoebeet4U.com
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP − (θJA x PD-MAX).
Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 12: Low-ESR Surface-Mount Ceramic Capacitors are used in setting electrical characteristics.
Note 13: Audio block inactive.
Note 14: In single-ended and in differential mode one audio buffer only is active and IVDDA will be reduced by 90 µA (typ).
Note 15: VREF pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between VREF and GND1.
5 www.national.com
5 Page 
I2C Compatible Interface (Continued)
www.DataSheet4U.com
20129311
FIGURE 6. Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9th clock pulse, signifying an acknowl-
edge. A receiver which has been addressed must generate
an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3950
address is 50’h or 51’h. The selection of the address is done
by connecting SI pin to VDDIO (51 hex) or GND (50 hex). For
the eighth bit, a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the
data will be written. The third byte contains data to write to
the selected register.
FIGURE 7. I2C Chip Address
20129312
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address, 50’h or 51’h for LP3950.
FIGURE 8. I2C Write Cycle
When a READ function is to be accomplished, a WRITE
function must precede the READ function, as shown in
Figure 9 .
11
20129313
www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LP3950.PDF ] | |
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