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PDF MC74HC533A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC533A | |
| Descripción | Octal 3-State Inverting Transparent Latch | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74HC533A (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State
Inverting Transparent Latch
High–Performance Silicon–Gate CMOS
The MC54/74HC533A is identical in pinout to the LS533. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The Data appears at the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC533A is identical in function to the HC563 but has the data inputs
on the opposite side of the package from the outputs to facilitate PC board
layout.
This device is similar in function to the HC373A, which has noninverting
outputs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 256 FETs or 64 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
INVERTING
OUTPUTS
LATCH ENABLE 11
OUTPUT ENABLE 1
PIN 20 = VCC
PIN 10 = GND
MC54/74HC533A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
1
2
20 VCC
19 Q7
D0 3
18 D7
D1 4
17 D6
Q1 5
16 Q6
Q2 6
15 Q5
D2 7
14 D5
D3 8
13 D4
Q3 9
GND 10
12 Q4
11 LATCH
ENABLE
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable D
Q
L HH L
L HL H
L L X No Change
H XX Z
X = Don’t Care
Z = High Impedance
3/97
© Motorola, Inc. 1997
1
REV 3
1 page  
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 5.
MC54/74HC533A
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH
* Includes all probe and jig capacitance
Figure 6.
LATCH 11
ENABLE
OUTPUT 1
ENABLE
D0
3
DQ
EXPANDED LOGIC DIAGRAM
D1 D2 D3 D4
4 7 8 13
DQ
DQ
DQ
DQ
D5
14
DQ
D6
17
DQ
D7
18
DQ
LE LE LE LE LE LE LE LE
2
5
6
9
12 15
16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC74HC533A.PDF ] | |
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