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PDF MM74HC589M Data sheet ( Hoja de datos )
| Número de pieza | MM74HC589M | |
| Descripción | 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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September 1983
Revised February 1999
MM74HC589
8-Bit Shift Registers with Input Latches and 3-STATE
Serial Output
General Description
The MM74HC589 high speed shift register utilizes
advanced silicon-gate CMOS technology to achieve the
high noise immunity and low power consumption of stan-
dard CMOS integrated circuits, as well as the ability to
drive 15 LS-TTL loads.
The MM74HC589 comes in a 16-pin package and consists
of an 8-bit storage latch feeding a parallel-in, serial-out 8-
bit shift register. Data can also be entered serially the shift
register through the SER pin. Both the storage register and
shift register have positive-edge triggered clocks, RCK and
SCK, respectively. SLOAD pin controls parallel LOAD or
serial shift operations for the shift register. The shift register
has a 3-STATE output to enable the wire-ORing of multiple
devices on a serial bus.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s 8-bit parallel storage register inputs
s Wide operating voltage range: 2V–6V
s Shift register has direct overriding load
s Guaranteed shift frequency. . . DC to 30 MHz
s Low quiescent current: 80 µA maximum (74HC Series)
s 3-STATE output for ‘Wire-OR'
Ordering Code:
Order Number Package Number
Package Description
MM74HC589M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC589SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC589MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC589N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
RCK SCK SLOAD OE
Function
XX
XX
↑X
X H QH in Hi-Z State
X L QH is enabled
X X Data loaded into input latches
↑X
L X Data loaded into shift register
from pins
H or L X
L X Data loaded from latches to
shift register
X↑
H X Shift register is shifted. Data
on SER pin is shifted in.
↑↑
H X Data is shifted in shift register,
and data is loaded into latches
© 1999 Fairchild Semiconductor Corporation DS005368.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = −40 to 85°C TA = −55 to 125°C Units
Typ Guaranteed Limits
tr, tf Maximum Input Rise and
Fall Time, Clock
2.0V
4.5V
1500
500
1500
500
1500
500
ns
ns
6.0V
400 400
400 ns
tTHL, tTLH Maximum Output
Rise and Fall Time
2.0V
4.5V
25
6
60
12
75
15
90 ns
18 ns
6.0V
5
10
12
15 ns
CPD Power Dissipation
Capacitance (Note 5)
87
pF
CIN Maximum Input Capacitance
5 10
10
10
COUT
Maximum Output Capacitance
15 20
20
20
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC sf + ICC.
pF
pF
5 www.fairchildsemi.com
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MM74HC589M.PDF ] | |
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