PDF SL74HC4052 Data sheet ( Hoja de datos )

Número de pieza	SL74HC4052
Descripción	Analog Multiplexer/Demultiplexer(High-Performance Silicon-Gate CMOS)
Fabricantes	System Logic Semiconductor
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No Preview Available ! SL74HC4052 Analog Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS The SL74HC4052 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input.When the Enable pin is high, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS TTLoutputs. • Fast Switching and Propagation Speeds • Low Crosstalk Between Switches • Diode Protection on All Inputs/Outputs • Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V • Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V • Low Noise ORDERING INFORMATION SL74HC4052N Plastic SL74HC4052D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM Double-Pole, 4-Position Plus Commo n Off PIN 16 =VCC PIN 7 = VEE PIN 8 = GND FUNCTION TABLE Control Inputs Enable Select BA L LL L LH L HL L HH HX X = don’t care X ON Channels Y0 X0 Y1 X1 Y2 X2 Y3 X3 None SLS System Logic Semiconductor 1 page SL74HC4052 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V) VCC Symbol BW Parameter Maximum On- Channel Bandwidth or Minimum Frequency Response (Figure 5) Test Conditions fin=1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequence Until dB Meter Reads -3 dB RL =50 Ω, CL=10 pF V 2.25 4.50 6.00 - Off-Channel fin= Sine Wave Feedthrough Adjust fin Voltage to Obtain 0 dBm at VIS Isolation fin = 10 kHz, RL =600 Ω, CL=50 pF (Figure 6) 2.25 4.50 6.00 fin = 1.0 MHz, RL =50 Ω, CL=10 pF 2.25 4.50 6.00 - Feedthrough VIN≤ 1 MHz Square Wave (tr = tf = 6 ns) Noise, Channel Adjust RL at Setup so that IS= 0 A Enable = Select Input to GND Common O/I (Figure 7) RL =600 Ω, CL=50 pF 2.25 4.50 6.00 RL =10 Ω, CL=10 pF 2.25 4.50 6.00 - Crosstalk fin= Sine Wave Between Any Adjust fin Voltage to Obtain 0 dBm at VIS Two Switches fin = 10 kHz, RL =600 Ω, CL=50 pF (Figure 14) 2.25 4.50 6.00 fin = 1 MHz, RL =50 Ω, CL=10 pF 2.25 4.50 6.00 THD Total Harmonic Distortion (Figure 16) fin= 1 kHz, RL =10 kΩ, CL=50 pF THD = THDMeasured - THDSource VIS =4.0 VPP sine wave VIS =8.0 VPP sine wave VIS =11.0 VPP sine wave * Limits not tested. Determined by design and verified by qualification. 2.25 4.50 6.00 VEE V -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 Limit* 25 °C Unit MHz 95 95 95 dB -50 -50 -50 -40 -40 -40 mVpp 25 105 135 35 145 190 dB -50 -50 -50 -60 -60 -60 % 0.10 0.08 0.05 SLS System Logic Semiconductor 5 Page

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Número de pieza	Descripción	Fabricantes
SL74HC4051	Analog Multiplexer Demultiplexer	System Logic Semiconductor
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SL74HC4051N	Analog Multiplexer Demultiplexer	System Logic Semiconductor
SL74HC4052	Analog Multiplexer/Demultiplexer(High-Performance Silicon-Gate CMOS)	System Logic Semiconductor

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