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PDF MC74ACT74 Data sheet ( Hoja de datos )
| Número de pieza | MC74ACT74 | |
| Descripción | Dual D-Type Positive Edge-Triggered Flip-Flop | |
| Fabricantes | ON Semiconductor | |
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MC74AC74, MC74ACT74
Dual D−Type Positive
Edge−Triggered Flip−Flop
The MC74AC74/74ACT74 is a dual D−type flip−flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
• Outputs Source/Sink 24 mA
• ′ACT74 Has TTL Compatible Inputs
• Pb−Free Packages are Available
VCC CD2 D2 CP2 SD2 Q2
14 13 12 11 10 9
Q2
8
D1 CD1 Q1
CP1 SD1 Q1
CP2 SD2 Q2
D2 CD2 Q2
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14
1
14
1
PDIP−14
N SUFFIX
CASE 646
SOIC−14
D SUFFIX
CASE 751A
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
1
SOEIAJ−14
M SUFFIX
CASE 965
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1234567
CD1 D1 CP1 SD1 Q1 Q1 GND
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN FUNCTION
D1, D2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q1, Q2,
Q2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1
Publication Order Number:
MC74AC74/D
1 page  
MC74AC74, MC74ACT74
DC CHARACTERISTICS
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
74ACT
74ACT
VCC
(V)
TA = +25°C
TA =
−40°C to
+85°C
Typ Guaranteed Limits
4.5 1.5 2.0
5.5 1.5 2.0
2.0
2.0
4.5 1.5 0.8
5.5 1.5 0.8
0.8
0.8
4.5 4.49 4.4
5.5 5.49 5.4
4.4
5.4
VOL Maximum Low Level
Output Voltage
4.5 − 3.86
5.5 − 4.86
4.5 0.001 0.1
5.5 0.001 0.1
3.76
4.76
0.1
0.1
4.5 −
5.5 −
IIN Maximum Input
Leakage Current
5.5 −
DICCT
IOLD
IOHD
Additional Max. ICC/Input
†Minimum Dynamic
Output Current
5.5 0.6
5.5 −
5.5 −
ICC Maximum Quiescent
Supply Current
5.5 −
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
0.36
0.36
±0.1
−
−
−
4.0
0.44
0.44
±1.0
1.5
75
−75
40
Unit Conditions
V
VOUT = 0.1 V
or VCC − 0.1 V
V
VOUT = 0.1 V
or VCC − 0.1 V
V IOUT = −50 mA
*VIN = VIL or VIH
V
IOH
−24 mA
−24 mA
V IOUT = 50 mA
*VIN = VIL or VIH
V IOL
24 mA
24 mA
mA VI = VCC, GND
mA VI = VCC − 2.1 V
mA VOLD = 1.65 V Max
mA VOHD = 3.85 V Min
mA VIN = VCC or GND
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
Min Typ Max
TA = −40°C
to +85°C
CL = 50 pF
Min Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
5.0 145 210 − 125 − MHz 3−3
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
tPLH
Propagation Delay
CPn to Qn or Qn
tPHL
Propagation Delay
CPn to Qn or Qn
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
5.0 3.0 5.5 9.5 2.5 10.5
5.0 3.0 6.0 10.0 3.0 11.5
5.0 4.0 7.5 11.0 4.0 13.0
5.0 3.5 6.0 10.0 3.0 11.5
ns
ns
ns
ns
3−6
3−6
3−6
3−6
http://onsemi.com
5
5 Page 
MC74AC74, MC74ACT74
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
0.15 (0.006) T U S
2X L/2 14
L
PIN 1
IDENT.
1
14X K REF
0.10 (0.004) M T U S V S
N
8
B
−U− N
0.25 (0.010)
M
F
7 DETAIL E
0.15 (0.006) T U S
A
−V−
ÇÇÇÉÉÇÇÇÉÉÇÇÇÉÉJ J1
K
K1
SECTION N−N
0.10 (0.004)
−T− SEATING
PLANE
D
C
G
H DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
−W−
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MC74ACT74.PDF ] | |
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