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PDF MC74HC564A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC564A | |
| Descripción | Octal 3-State Inverting D Flip-Flop | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74HC564A (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State
Inverting D Flip-Flop
High–Performance Silicon–Gate CMOS
The MC74HC564A is identical in pinout to the LS564. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is identical in function to the HC534A but has the flip–flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
Data meeting the setup time is clocked, in inverted form, to the outputs
with the rising edge of the Clock. The Output Enable input does not affect the
states of the flip–flops, but when Output Enable is high, all device outputs are
forced to the high–impedance state. Thus, data may be stored even when
the outputs are not enabled.
The HC564A is the inverting version of the HC574A.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 282 FETs or 70.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
CLOCK 11
OUTPUT 1
ENABLE
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
INVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
MC74HC564A
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC74HCXXXAN Plastic
MC74HCXXXADW SOIC
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
1
2
20 VCC
19 Q0
D1 3
18 Q1
D2 4
17 Q2
D3 5
16 Q3
D4 6
15 Q4
D5 7
14 Q5
D6 8
13 Q6
D7 9
12 Q7
GND 10
11 CLOCK
FUNCTION TABLE
Output
Enable
L
L
L
H
Inputs
Clock
L,H,
X
Output
DQ
HL
LH
X No Change
XZ
X = don’t care
Z = high impedance
9/96
© Motorola, Inc. 1996
1
REV 0
1 page  
tr tf
CLOCK
Q
90%
50%
10%
tw
90%
50%
10%
1/fmax
tPLH tPHL
tTLH tTHL
Figure 1.
MC74HC564A
SWITCHING WAVEFORMS
VCC
OUTPUT
50%
VCC
GND ENABLE
GND
tPZL tPLZ
HIGH
Q
50%
tPZH tPHZ
IMPEDANCE
10% VOL
90% VOH
Q 50%
HIGH
IMPEDANCE
Figure 2.
DATA
CLOCK
VALID
50%
tsu th
50%
Figure 3.
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 4.
* Includes all probe and jig capacitance
Figure 5.
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74HC564A.PDF ] | |
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