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PDF MC100E131 Data sheet ( Hoja de datos )
| Número de pieza | MC100E131 | |
| Descripción | 4-BIT D FLIP-FLOP | |
| Fabricantes | ON Semiconductor | |
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MC10E131, MC100E131
5 V ECL 4‐Bit D Flip‐Flop
Description
The MC10E/100E131 is a quad master-slave D-type flip-flop with
differential outputs. Each flip-flop may be clocked separately by
holding Common Clock (CC) LOW and using the Clock Enable (CE)
inputs for clocking. Common clocking is achieved by holding the CE
inputs LOW and using CC to clock all four flip-flops. In this case, the
CE inputs perform the function of controlling the common clock, to
each flip-flop.
Individual asynchronous resets are provided (R). Asynchronous set
controls (S) are ganged together in pairs, with the pairing chosen to
reflect physical chip symmetry.
Data enters the master when both CC and CE are LOW, and transfers
to the slave when either CC or CE (or both) go HIGH.
The 100 Series contains temperature compensation.
www.onsemi.com
PLCC−28
FN SUFFIX
CASE 776−02
Features
• 1100 MHz Min. Toggle Frequency
• Differential Outputs
• Individual and Common Clocks
• Individual Resets (asynchronous)
• Paired Sets (asynchronous)
• PECL Mode Operating Range:
♦ VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range:
♦ VCC = 0 V with VEE = −4.2 V to −5.7 V
• Metastability Time Constant is 200 ps.
• Internal Input 50 kW Pulldown Resistors
• ESD Protection:
♦ Human Body Model; > 2 kV
♦ Machine Model; > 200 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level: 3 (Pb-Free)
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating:UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 240 devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
MARKING DIAGRAM*
1
MCxxxE131G
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
MC10E131FNG
MC10E131FNR2G
MC100E131FNG
MC100E131FNR2G
Package
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
Shipping†
37 Units/Tube
500/Tape & Reel
37 Units/Tube
500/Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 12
1
Publication Order Number:
MC10E131/D
1 page  
MC10E131, MC100E131
Table 6. 100E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1))
−40°C
0°C
25°C
85°C
Symbol
IEE
VOH
VOL
Characteristic
Power Supply Current
Output HIGH Voltage
(Note 2)
Output LOW Voltage
(Note 2)
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
58 70
58 70
58 70
67 81 mA
−1025 −950 −880 −1025 −950 −880 −1025 −950 −880 mV
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIH Input HIGH Current
CC
S
R, CE
D
−1025
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV
−1645
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV
mA
350 350 350 350
450 450 450 450
300 300 300 300
150 150 150 150
IIL Input LOW Current
0.5 0.3
0.5 0.25
0.5 0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
2. Outputs are terminated through a 50ĂW resistor to VCC − 2.0 V.
Table 7. AC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 1))
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
fMAX
tPLH
tPHL
Maximum Toggle Frequency
Propagation Delay to Output
CE
CC
R
S
1100 1400
1100 1400
1100 1400
MHz
310 600 750 360 500 700 360 500 700
275 600 725 325 500 675 325 500 675
400 635 875 450 640 825 450 640 825
300 550 775 350 550 725 350 550 725
ps
tS Setup Time (Note 2)
D
200 20
150 20
150 20
ps
tH Hold Time (Note 2)
D
225 −20
175 −20
175 −20
ps
tRR Reset Recovery Time
tPW Minimum Pulse Width
CLK
R, S
450 150
400
400
400 150
400
400
400 150
400
400
ps
ps
tSKEW
tJITTER
tr/tf
Within-Device Skew (Note 3)
Random Clock Jitter
Rise/Fall Time (20−80%)
60 60
<1 <1
275 460 725 300 480
60
<1
300 480 675
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
2. Setup/hold times guaranteed for both CC and CE.
3. Within-device skew is defined as identical transitions on similar paths through a device.
www.onsemi.com
5
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| PDF Descargar | [ Datasheet MC100E131.PDF ] | |
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