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Quiet Seriesa 9-Bit D-Type Flip-Flop with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ACTQ823SPC 데이터시트, 핀배열, 회로
May 1991
Revised December 1998
74ACTQ823
Quiet Series9-Bit D-Type Flip-Flop
with 3-STATE Outputs
General Description
The ACTQ823 is a 9-bit buffered register. It features Clock
Enable and Clear which are ideal for parity bus interfacing
in high performance microprogramming systems. The
ACTQ823 utilizes Fairchild Quiet Seriestechnology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Improved latch-up immunity
s Has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ823SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ823SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
IEEE/IEC
Pin Descriptions
Pin Names
D0–D8
O0–O8
OE
CLR
CP
EN
Description
Data Inputs
Data Outputs
Output Enable
Clear
Clock Input
Clock Enable
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010921.prf
www.fairchildsemi.com


74ACTQ823SPC 데이터시트, 핀배열, 회로
Functional Description
The ACTQ823 consists of nine D-type edge-triggered flip-
flops. These have 3-STATE outputs for bus systems orga-
nized with inputs and outputs on opposite sides. The buff-
ered clock (CP) and buffered Output Enable (OE) are
common to all flip-flops. The flip-flops will store the state of
their individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH CP transition. With OE
LOW, the contents of the flip-flops are available at the out-
puts. When OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR) and Clock Enable (EN)
pins. These devices are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the
EN is HIGH, the outputs do not change state, regardless of
the data or clock input transitions.
Function Table
Inputs
OE CLR EN
HX L
HX L
HLX
LLX
HHH
L HH
HHL
HHL
LHL
LHL
CP
X
X
X
X
D
L
H
X
X
X
X
L
H
L
H
Internal
Q
L
H
L
L
NC
NC
L
H
L
H
Output
O
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74ACTQ823SPC flip-flop

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Quiet Seriesa 9-Bit D-Type Flip-Flop with 3-STATE Outputs - Fairchild Semiconductor