Revised December 1998
Quiet Series™ 9-Bit D-Type Flip-Flop
with 3-STATE Outputs
The ACTQ823 is a 9-bit buffered register. It features Clock
Enable and Clear which are ideal for parity bus interfacing
in high performance microprogramming systems. The
ACTQ823 utilizes Fairchild Quiet Series™ technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addition
to a split ground bus for superior performance.
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Improved latch-up immunity
s Has TTL-compatible inputs
Order Number Package Number
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.
for DIP and SOIC
FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010921.prf
The ACTQ823 consists of nine D-type edge-triggered flip-
flops. These have 3-STATE outputs for bus systems orga-
nized with inputs and outputs on opposite sides. The buff-
ered clock (CP) and buffered Output Enable (OE) are
common to all flip-flops. The flip-flops will store the state of
their individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH CP transition. With OE
LOW, the contents of the flip-flops are available at the out-
puts. When OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR) and Clock Enable (EN)
pins. These devices are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the
EN is HIGH, the outputs do not change state, regardless of
the data or clock input transitions.
OE CLR EN
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.