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PDF NJU6655 Data sheet ( Hoja de datos )
| Número de pieza | NJU6655 | |
| Descripción | 64-common X 160-segment + 1-icon common Bitmap LCD Driver | |
| Fabricantes | NJR | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NJU6655 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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www.DataSheet4U.com
NJU6655
Preliminary
64-common X 160-segment + 1-icon common
Bitmap LCD Driver
! GENERAL DESCRIPTION
The NJU6655 is a bitmap LCD driver to display graphics or
characters.
It contains 10,400 bits display data RAM, microprocessor
interface circuits, instruction decoder, 64-common and
160-segment + 1-icon-common drivers.
The bit image display data is transferred to the display data
RAM by serial or 8-bit parallel interface.
65 x 160 dots graphics or 10-character 4-line by 16 x 16 dots
character with icon are displayed by NJU6655 itself.
The wide operating voltage from 2.4 to 5.5V and low operating
current are suitable for battery-powered applications.
The build-in Electrical Variable Resistance is very precision,
furthermore the rectangle outlook is very applicable to COG or
Slim TCP.
! PACKAGE OUTLINE
NJU6655CJ
! FEATURES
# Direct Correspondence between Display Data RAM and LCD Pixel
# Display Data RAM - 10,400 bits
# 225 LCD Drivers - 64-common and 160-segment + 1-icon common
# Direct Microprocessor Interface for both of 68 and 80 type MPU
# Serial Interface (SI, SCL, A0, CS1b, CS2)
# Programmable Bias selection : 1/5,1/7,1/9 bias
# Useful Instruction Set
Display On/Off Cont, Initial Display Line Set, Page Address Set, Column Address Set, Status Read,
Display Data Read/Write, ADC Select, Inverse Display, Entire Display On/Off, Bias Select, Read Modify Write,
End, Reset, Common Direction Register Set, Power control set, Feedback Resistor Ratio Set,
EVR Mode Set, EVR Register Set, Static Indicator On/Off, Static Indicator Register Set, Power Save,
Power Save Reset, n-line Inverse Drive Register Set, n-line Inverse Drive Reset, Partial Select,
Internal Oscillation Circuit ON.
# Power Supply Circuits for LCD Incorporated
Voltage Booster Circuits (4-time Maximum),
Voltage Adjust Circuits, Voltage Follower x 4
# Voltage Regulator Incorporated
# Precision Electrical Variable Resistance (64-step)
# Low Power Consumption T.B.D.uA(Typ.).
# Operating Voltage (All the voltages are based on VDD=0V.)
- Logic Operating Voltage
: -2.4V to -5.5V
- Voltage Booster Operating Voltage
: -2.4V to -6.0V
- LCD Driving Voltage
: -4.5V to -18.0V
# Rectangle outlook for COG
# Package Outline : Bump-chip
# C-MOS Technology (Substrate : N)
Ver.2004-11-08
DataSheet4 U .com
-1-
1 page  
www.DataSheet4U.com
NJU6655
PAD No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Terminal
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
X= um
465
415
365
315
265
215
165
115
65
15
-35
-85
-135
-185
-235
-285
-335
-385
-435
-485
-535
-585
-635
-685
-735
-785
-835
-885
-935
-985
-1035
-1085
-1135
-1185
-1235
-1285
-1335
-1385
-1435
-1485
-1535
-1585
-1635
-1685
-1735
-1785
-1835
-1885
-1935
-1985
Y= um
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
PAD No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Terminal
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
DUMMY17
DUMMY18
DUMMY19
DUMMY20
DUMMY21
DUMMY22
S157
S158
S159
C32
C33
C34
C35
C36
C37
C38
X= um
-2035
-2085
-2135
-2185
-2235
-2285
-2335
-2385
-2435
-2485
-2535
-2585
-2635
-2685
-2735
-2785
-2835
-2885
-2935
-2985
-3035
-3085
-3135
-3185
-3235
-3285
-3335
-3385
-3435
-3485
-3535
-3585
-3635
-3685
-4015
-4065
-4115
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
Y= um
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1063
1013
963
913
863
813
763
713
663
613
563
513
463
Ver.2004-11-08
DataSheet4 U .com
-5-
5 Page 
www.DataSheet4U.com
NJU6655
! FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Busy Flag (BF)
During internal operation, the LSI is being busy and can’t accept any instructions except “status read”. The BF
data is output through D7 terminal by the “status read” instruction.
When the cycle time (tcyc) mentioned in the “AC characteristics” is satisfied, the BF check isn’t required after
each instruction, so that MPU processing performance can be improved.
(1-2) Initial display line register
The initial display line register assigns a DDRAM line address, which corresponds to COM0 by “initial display
line set” instruction. It is used for not only normal display but also vertical display scrolling and page switching
without changing the contents of the DDRAM.
However, the 65th address for icon display can’t be assigned for initial display line address.
(1-3) Line counter
The line counter provides a DDRAM line address. It initializes its contents at the switching of frame timing signal
(FR), and also counts-up in synchronization with common timing signal.
(1-4) Column address counter
The column address counter is an 8-bit preset counter, which provides a DDRAM column address, and it is
independent of below-mentioned page address register.
It will increment (+1) the column address whenever “display data read” or “display data write” instructions are
issued. However, the counter will be locked when no-existing address above A0H are addressed. The count-lock will
be able to be released by the “column address set” instruction again. The counter can invert the correspondence
between the column address and segment driver direction by means of “ADC set” instruction.
(1-5) Page address register
The page address register provides a DDRAM page address.
The last page address “8” should be used for icon display because the only D0 is valid.
(1-6) Display data RAM (DDRAM)
The DDRAM contains 10,400-bit, and stores display data, which are 1-to-1 correspondents to LCD panel pixels.
When normal display mode, the display data “1” turns on and “0” turns off LCD pixels. When inverse display
mode, “1” turns off and “0” turns on.
Ver.2004-11-08
DataSheet4 U .com
- 11 -
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NJU6655.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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