PDF MPC99J93 Data sheet ( Hoja de datos )

Número de pieza	MPC99J93
Descripción	Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNFIrCeAeLsDcAaTAle Semiconductor, Inc. Order Number: MPC99J93/D Rev 1, 08/2003 Product Preview Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver MPC99J93 The MPC99J93 is a PLL clock driver designed specifically for redun- dant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. Features: • Fully Integrated PLL • Intelligent Dynamic Clock Switch • LVPECL Clock Outputs • LVCMOS Control I/O • 3.3V Operation • 32--Lead LQFP Packaging FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A Functional Description The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section). Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset PLL_En Dynamic Switch Logic Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR OR PLL 200 -- 360 MHz ÷2 ÷4 Figure 1. Block Diagram Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. E Motorola Inc. 2003 MOTOROLA TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com 1 1 page Freescale Semiconductor, Inc. MPC99J93 Table 5. AC Characteristics (VCC = 3.3V ± 5%, TA = --40°C to +85°C)a Symbol Characteristics Min Typ Max Unit Condition fref fVCO fMAX Input Reference Frequency VCO Frequency Rangeb Output Frequency ÷4 feedback ÷4 feedback QA[1:0] QB[2:0] 50 200 50 100 90 MHz PLL locked 360 MHz 90 MHz PLL locked 180 MHz frefDC t(∅) Reference Input Duty Cycle Propagation Delay SPO, static phase offsetc CLK0, CLK1 to any Q 25 -0.15 0.9 75 +0.17 1.8 % ns PLL_EN=1 ns PLL_EN=0 VPP VCMR tsk(O) Differential input voltaged (peak-to-peak) Differential input crosspoint voltagee Output-to-output Skew within QA[2:0] or QB[1:0] within device 0.25 VCC-1.7 1.3 VCC-0.3 50 80 V V ps ps ∆per/cycle Rate of change of period QA[1:0]f QB[2:0]f QA[1:0]g QB[2:0]g 20 50 ps 10 25 ps 200 400 ps 100 200 ps DC Output Duty Cycle 45 50 55 % tJIT(CC) Cycle-to-Cycle Jitter RMS (1 σ) 25 ps tLOCK Maximum PLL Lock Time 10 ms tr, tf Output Rise/Fall Time 0.05 0.70 ns 20% to 80% a. AC characteristics apply for parallel output termination of 50Ω to VCC - 2V. b. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): fref = fVCO ÷ FB. c. CLK0, CLK1 to Ext_FB. d. VPP is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew. Ap- plicable to CLK0, CLK1 and Ext_FB. e. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the SPO, device and part-to- part skew. Applicable to CLK0, CLK1 and Ext_FB. f. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. g. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (±180_). Delta period change per cycle is averaged over the clock switch excursion. MOTOROLA TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com 5 5 Page

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