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PDF MC14544B Data sheet ( Hoja de datos )
| Número de pieza | MC14544B | |
| Descripción | BCD-to-Seven Segment Latch/Decoder/Driver for Liquid Crystals | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC14544B (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
BCD-to-Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
CMOS MSI (Low–Power Complementary MOS)
The MC14544B BCD–to–seven segment latch/decoder/driver is designed
for use with liquid crystal readouts, and is constructed with complementary
MOS (CMOS) enhancement mode devices. The circuit provides the
functions of a 4–bit storage latch and an 8421 BCD–to–seven segment
decoder and driver. The device has the capability to invert the logic levels of
the output combination. The phase (Ph), blanking (BI), and latch disable (LD)
inputs are used to reverse the truth table phase, blank the display, and store
a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is
applied to the Ph input of the circuit and the electrically common backplane
of the display. The outputs of the circuit are connected directly to the
segments of the LC readout. The Ripple Blanking Input (RBI) and the Ripple
Blanking Output (RBO) can be used to suppress either leading or trailing
zeroes.
For other types of readouts, such as light–emitting diode (LED),
incandescent, gas discharge, and fluorescent readouts, connection dia-
grams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.
• Latch Storage of Code
• Blanking Input
• Readout Blanking on All Illegal Input Combinations
• Direct LED (Common Anode or Cathode) Driving Capability
• Supply Voltage Range = 3.0 V to 18 V
• Capability for Suppression of Non–significant zero
• Capable of Driving Two Low–power TTL Loads, One Low–power
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSchottky TTL Load or Two HTL Loads Over the Rated Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRange
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRating
Symbol
Value
Unit
DC Supply Voltage
VDD
– 0.5 to + 18
V
Input Voltage, All Inputs
Vin – 0.5 to VDD + 0.5 V
DC Input Current per Pin
Iin ± 10 mAdc
Operating Temperature Range
TA
– 55 to + 125
_C
Power Dissipation, per Package† PD 500 mW
Storage Temperature Range
Tstg
– 65 to + 150
_C
Maximum Continuous Output Drive
Current (Source or Sink) per Output
IOHmax
IOLmax
10 mAdc
Maximum Continuous Output Power*
(Source or Sink) per Output
POHmax
POLmax
70
mW
* POHmax = IOH (VOH – VDD) and POLmax = IOL (VOL – VSS)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14544B
L SUFFIX
CERAMIC
CASE 726
P SUFFIX
PLASTIC
CASE 707
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
Plastic
Ceramic
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
LD 1
C2
B3
D4
A5
PH 6
BI 7
RBO 8
VSS 9
18 VDD
17 f
16 g
15 e
14 d
13 c
12 b
11 a
10 RBI
a
f gb
ec
d
DISPLAY
012 345 6789
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v voperation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
MC14544B
1
1 page  
0
POHmax = 70 mWdc
VDD = 5.0 Vdc
– 6.0
– 12 VDD = 10 Vdc
– 18
VDD = 15 Vdc
– 24
– 16
VSS = 0 Vdc
– 12 – 8.0 – 4.0
(VOH – VDD), SOURCE DEVICE VOLTAGE (Vdc)
Figure 1. Typical Output Source
Characteristics
0
Inputs BI and Ph low, and Inputs D and LD high.
f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns
20 ns
A, B, AND C
10%
90% 50%
1
2f
50% DUTY CYCLE
ANY OUTPUT
VDD
VSS
VOH
VOL
Figure 3. Dynamic Power Dissipation
Signal Waveforms
24
VDD = 15 Vdc
18
12 VDD = 10 Vdc
6.0
0
0
VDD = 5.0 Vdc
POLmax = 70 mWdc
VSS = 0 Vdc
4.0 8.0 12
(VOL – VSS), SINK DEVICE VOLTAGE (Vdc)
16
Figure 2. Typical Output Sink
Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.
20 ns
20 ns
C 90% 50%
10%
tPHL tPLH
g
90% 50%
10%
tTHL tTLH
VDD
VSS
VOH
VOL
(b) Inputs D, Ph, and BI low, and Inputs A and B high.
20 ns
LD 90% 50%
10%
tsu
th
C 50%
50%
VDD
VSS
VDD
VSS
VOH
g
VOL
(c) Data DCBA strobed into latches
LD 50%
tWH
VDD
VSS
Figure 4. Dynamic Signal Waveforms
MOTOROLA CMOS LOGIC DATA
MC14544B
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC14544B.PDF ] | |
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