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PDF PI6C2972FCE Data sheet ( Hoja de datos )

Número de pieza PI6C2972FCE
Descripción Low Voltage PLL Clock Driver
Fabricantes Pericom Semiconductor Corporation 
Logotipo Pericom Semiconductor Corporation Logotipo



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No Preview Available ! PI6C2972FCE Hoja de datos, Descripción, Manual

PI6C2972
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Low Voltage PLL Clock Driver
Features
• Fully Integrated PLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• 3.3VVCC
• + 100ps Typical Cycle–to–Cycle Jitter
• Packaging (Pb-free & Green available):
- 52-pin LQFP (FC)
Pin Configuration
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GND0
VCO_Sel
39 38 37 36 35 34 33 32 31 30 29 28 27
40 26
41 25
42 24
43 23
44 22
45 21
46 20
47 19
48 18
49 17
50 16
51 15
52 14
1 2 3 4 5 6 7 8 9 10 11 12 13
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GND0
Inv_Clk
Description
The PI6C2972 are 3.3V compatible, PLL based clock driver devices
targeted for high-performance CISC or RISC processor based sys-
tems. With output frequencies of up to 125 MHz and skews of 550ps
the PI6C2972 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync
output for added flexibility and ease of system implementation.
The PI6C2972 features an extensive level of frequency programma-
bility between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1,
2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges
of the Qa and Qc outputs. The Sync output will indicate when the
coincident rising edges of the above relationships will occur. The
Power–On Reset ensures proper programming if the frequency
select pins are set at power up. If the fselFB2 pin is held high, it may
be necessary to apply a reset after power–up to ensure synchroni-
zation between the QFB output and the other outputs. The internal
power–on reset is designed to provide this function, but with
power–up conditions being dependent, it is difficult to guarantee.
All other conditions of the fsel pins will automatically synchronize
during PLL lock acquisition.
The PI6C2972 offers a very flexible output enable/disable scheme.
Note that all of the control inputs on the PI6C2972 have internal pull–
up resistors.
The PI6C2972 is fully 3.3V compatible and requires no external loop
filter components. All inputs accept LVCMOS/LVTTL compatible
levels while the outputs provide LVCMOS levels with the capability
to drive 50-ohm transmission lines. For series terminated lines each
PI6C2972 output can drive two 50-ohm lines in parallel thus effec-
tively doubling the fanout of the device.
1 PS8590C 09/22/04

1 page




PI6C2972FCE pdf
PI6C2972
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233L4455o6677w8899V001122o33l44t55a6677g88e9900P1122L3344L556677C8899l00o11c2211k2233D4455r6677iv8899e00r1122
Absolute Maximum Ratings
Symbol
VCC
VI
IIN
TSTOR
Parameter
Supply Voltage
Input Voltage
Input Current
Storage Temperature
Min.
–0.3
–0.3
–40
Max.
4.6
VDD +0.3
±20
125
Units
V
V
mA
°C
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute-maximum-rated conditions is not implied.
DC Characteristics (TA = 0°C to 70°C, VCC = 3.3V ± 5%)(4)
Symbol
Conditions
Characteristic
Min.
Typ. Max.
VIH
Input HIGH Voltage
2.0
3.6
VIL
VOH
VOL
IOH = 20mA(2)
IOL = 20mA(2)
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
2.4
0.8
0.5
IIN Note 3
Input Current
±120
ICC
Maximum Quiescent Supply Current
190 215
ICCA
Analog VCC Current
15 20
CIN Input Capacitance
4
Cpd Per Output
Power Dissipation Capacitance
25
Notes:
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when
the “High” input is within the VCMR range and the input lies within the VPP specification.
2. The PI6C2972 outputs can drive series or parallel terminated 50 Ohm (or 50 Ohm to VCC/2) transmission lines on the
incident edge.
3. Inputs have pull–up/pull–down resistors which affect input current.
4. Special thermal handling may be required in some configurations.
Units
V
µΑ
mA
pF
5 PS8590C 09/22/04

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