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PDF DS90LV047ATM Data sheet ( Hoja de datos )
| Número de pieza | DS90LV047ATM | |
| Descripción | 3V LVDS Quad CMOS Differential Line Driver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1999
DS90LV047A
3V LVDS Quad CMOS Differential Line Driver
General Description
The DS90LV047A is a quad CMOS flow-through differential
line driver designed for applications requiring ultra low power
dissipation and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
The DS90LV047A accepts low voltage TTL/CMOS input lev-
els and translates them to low voltage (350 mV) differential
output signals. In addition, the driver supports a TRI-STATE®
function that may be used to disable the output stage, dis-
abling the load current, and thus dropping the device to an
ultra low idle power state of 13 mW typical. The
DS90LV047A has a flow-through pinout for easy PCB layout.
The EN and EN* inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four
drivers. The DS90LV047A and companion line receiver
(DS90LV048A) provide a new alternative to high power
psuedo-ECL devices for high speed point-to-point interface
applications.
Features
n >400 Mbps (200 MHz) switching rates
n Flow-through pinout simplifies PCB layout
n 300 ps typical differential skew
n 400 ps maximum differential skew
n 1.7 ns maximum propagation delay
n 3.3V power supply design
n ±350 mV differential signaling
n Low power dissipation (13mW at 3.3V static)
n Interoperable with existing 5V LVDS receivers
n High impedance on LVDS outputs on power down
n Conforms to TIA/EIA-644 LVDS Standard
n Industrial operating temperature range (−40˚C to +85˚C)
n Available in surface mount (SOIC) and low profile
TSSOP package
Connection Diagram
Dual-In-Line
Functional Diagram
DS100887-1
Order Number DS90LV047ATM, DS90LV047ATMTC
See NS Package Number M16A, MTC16
Truth Table
ENABLES
EN EN*
H L or Open
All other combinations of ENABLE inputs
DS100887-2
INPUT
DIN
L
H
X
OUTPUTS
DOUT+
L
DOUT−
H
HL
ZZ
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100887
www.national.com
1 page  
Parameter Measurement Information (Continued)
Typical Application
FIGURE 5. Driver TRI-STATE Delay Waveform
DS100887-7
DS100887-8
FIGURE 6. Point-to-Point Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 6. This configuration provides a clean signaling en-
vironment for the fast edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically, the characteristic differential
impedance of the media is in the range of 100Ω. A termina-
tion resistor of 100Ω (selected to match the media), and is lo-
cated as close to the receiver input pins as possible. The ter-
mination resistor converts the driver output current (current
mode) into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu-
ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.
The DS90LV047A differential line driver is a balanced cur-
rent source design. A current mode driver, generally speak-
ing has a high output impedance and supplies a constant
current for a range of loads (a voltage mode driver on the
other hand supplies a constant voltage for a range of loads).
Current is switched through the load in one direction to pro-
duce a logic state and in the other direction to produce the
other logic state. The output current is typically 3.1 mA, a
minimum of 2.5 mA, and a maximum of 4.5 mA. The current
mode driver requires (as discussed above) that a resistive
termination be employed to terminate the signal and to com-
plete the loop as shown in Figure 6. AC or unterminated con-
figurations are not allowed. The 3.1 mA loop current will de-
velop a differential voltage of 310mV across the 100Ω
termination resistor which the receiver detects with a 250mV
minimum differential noise margin, (driven signal minus re-
ceiver threshold (250mV – 100mV = 150mV)). The signal is
centered around +1.2V (Driver Offset, VOS) with respect to
ground as shown in Figure 7. Note that the steady-state volt-
age (VSS) peak-to-peak swing is twice the differential voltage
(VOD) and is typically 620mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
quency. Whereas the RS-422 voltage mode driver increases
exponentially in most case between 20 MHz–50 MHz. This
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the cur-
rent mode driver switches a fixed current between its output
without any substantial overlap current. This is similar to
some ECL and PECL devices, but without the heavy static
ICC requirements of the ECL/PECL designs. LVDS requires
> 80% less current than similar PECL devices. AC specifica-
tions for the driver are a tenfold improvement over other ex-
isting RS-422 drivers.
5 www.national.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC
Order Number DS90LV047ATM
NS Package Number M16A
11 www.national.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS90LV047ATM.PDF ] | |
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