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PDF CXD1268 Data sheet ( Hoja de datos )
| Número de pieza | CXD1268 | |
| Descripción | CCD Vertical Clock Driver | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CXD1268 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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CCD Vertical Clock Driver
CXD1268M
Description
The CXD1268M is a clock driver for CCD vertical
register drive.
Features
• On-chip 4-channel driver.
(Binary driver × 2, and trinary driver × 2)
• Low output ON resistance provides optimal drive
for large load capacity CCD.
Applications
CCD cameras
Structure
CMOS
Absolute Maximum Ratings (GND = 0V, Ta = 25°C)
• Supply voltage
• Supply voltage
VH
VL to VL + 25
V
VM
VL to VL + 17∗1
V
• Supply voltage
VDD GND to GND + 7 V
• Supply voltage
VL
GND – 10 to GND
V
• Input voltage
VI
–0.5 to VDD + 0.5
V
• Input/output clamp
diode current
IIC, IOC
–10 to +10
mA
• Maximum DC load current IODC
–3 to +3
mA
• Maximum load capacity
CL
to 30,000 pF/pin
• Allowable power dissipation PD
to 200
mW
• Storage temperature
∗1 Use VM at less than VDD.
Tstg
–60 to +150
°C
Recommended Operating Conditions
• Supply voltage
VH VM + 6.5 to VM + 15.5
• Supply voltage
VL VM – 10.0 to VM – 7.0
• Supply voltage
VM 0.0 to 4.0
• Supply voltage
• High level input voltage
• Low level input voltage
VDD
VIH∗2
VIL∗2
4.75 to 5.25
3.5 to VDD
0.0 to 1.0
• Operating temperature
∗2 VDD = 5V
Topr
–10 to +60
V
V
V
V
V
V
°C
20 pin SOP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96635-PS
1 page  
Waveform Diagram (1)
input
XV1 to XV4
output
Vφ1 to Vφ4
Waveform Diagram (2)
input
XSG1, XSG2
output
Vφ1, Vφ3
tr
10%
90%
50%
tPHL
90%
50%
10%
tTHL
tf
tPLH
tTLH
tr
90%
50%
10%
tPLH
50%
10%
90%
tTLH
tf
tPHL
tTHL
CXD1268M
VDD
GND
tr = tf = 20ns
VφM
VφL
VDD
GND
tr = tf = 20ns
VφH
VφM
Output Load Circuit Diagram
1600pF
Vφ1
3000pF
Vφ2
2000pF
1000pF
1000pF
2000pF
Vφ4
3000pF
Vφ3
1600pF
–5–
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CXD1268.PDF ] | |
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