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PDF SPC560P40L1 Data sheet ( Hoja de datos )
| Número de pieza | SPC560P40L1 | |
| Descripción | 32-bit Power Architecture based MCU | |
| Fabricantes | STMicroelectronics | |
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SPC560P34L1, SPC560P34L3
SPC560P40L1, SPC560P40L3
32-bit Power Architecture® based MCU with 320 KB Flash memory
and 20 KB RAM for automotive chassis and safety applications
Datasheet − production data
Features
■ Up to 64 MHz, single issue, 32-bit CPU core
complex (e200z0h)
– Compliant with Power Architecture®
embedded category
– Variable Length Encoding (VLE)
■ Memory organization
– Up to 256 KB on-chip code flash memory
with ECC and erase/program controller
– Additional 64 (4 × 16) KB on-chip data
flash memory with ECC for EEPROM
emulation
– Up to 20 KB on-chip SRAM with ECC
■ Fail-safe protection
– Programmable watchdog timer
– Non-maskable interrupt
– Fault collection unit
■ Nexus Class 1 interface
■ Interrupts and events
– 16-channel eDMA controller
– 16 priority level controller
– Up to 25 external interrupts
– PIT implements four 32-bit timers
– 120 interrupts are routed via INTC
■ General purpose I/Os
– Individually programmable as input, output
or special function
– 37 on LQFP64
– 64 on LQFP100
■ 1 general purpose eTimer unit
– 6 timers each with up/down capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
flag
– Double buffer input capture and output
compare
LQFP100 (14 x 14 x 1.4 mm)
LQFP64 (10 x 10 x 1.4 mm)
■ Communications interfaces
– 2 LINFlex channels (1× Master/Slave, 1×
Master only)
– Up to 3 DSPI channels with automatic chip
select generation (up to 8/4/4 chip selects)
– Up to 2 FlexCAN interface (2.0B Active)
with 32 message buffers
– 1 safety port based on FlexCAN with 32
message buffers and up to 8 Mbit/s at
64 MHz capability usable as second CAN
when not used as safety port
■ One 10-bit analog-to-digital converter (ADC)
– Up to 16 input channels (16 on LQFP100 /
12 on LQFP64)
– Conversion time < 1 µs including sampling
time at full precision
– Programmable Cross Triggering Unit (CTU)
– 4 analog watchdogs with interrupt
capability
■ On-chip CAN/UART bootstrap loader with Boot
Assist Module (BAM)
■ 1 FlexPWM unit: 8 complementary or
independent outputs with ADC synchronization
signals
Table 1. Device summary
Package
Code flash memory
192 KB
256 KB
LQFP100 SPC560P34L3 SPC560P40L3
LQFP64 SPC560P34L1 SPC560P40L1
September 2013
This is information on a product in full production.
Doc ID 16100 Rev 7
1/103
www.st.com
1
1 page  
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPC560P34/SPC560P40 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPC560P40 device configuration differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPC560P34/SPC560P40 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Approved NPN ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . 60
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . 62
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . 65
Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . 66
Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75
Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
DSPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Doc ID 16100 Rev 7
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5 Page 
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Introduction
Table 4.
SPC560P34/SPC560P40 series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM)
Block of read-only memory containing VLE code which is executed according to
the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Controller area network
(FlexCAN)
Supports the standard CAN communications protocol
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the
eMIOS or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width
Cyclic redundancy check (CRC) CRC checksum generator
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Enhanced direct memory access Performs complex data transfers with minimal intervention from a host
(eDMA)
processor via “n” programmable channels
Enhanced timer (eTimer)
Provides enhanced programmable up/down modulo counting
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
External oscillator (XOSC)
Provides an output clock used as input reference for FMPLL_0 or as reference
clock for specific modules depending on system needs
Fault collection unit (FCU)
Provides functional safety to the device
Flash memory
Provides non-volatile storage for program code, constants and variables
Frequency-modulated phase-
locked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Peripheral bridge (PBRIDGE) Is the interface between the system bus and on-chip peripherals
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Doc ID 16100 Rev 7
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SPC560P40L1.PDF ] | |
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