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PDF ADAR7251 Data sheet ( Hoja de datos )
| Número de pieza | ADAR7251 | |
| Descripción | 4-Channel / 16-Bit / Continuous Time Data Acquisition ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
4-Channel, 16-Bit, Continuous Time
Data Acquisition ADC
ADAR7251
FEATURES
Low noise: 2.4 nV/√Hz input referred voltage noise at
maximum gain setting
Wide input signal bandwidth: 500 kHz at 1.2 MSPS sample
rate, 16-bit resolution
Additional sample rates supported: 300 kSPS, 450 kSPS,
600 kSPS, 900 kSPS, and 1.8 MSPS
4 differential simultaneous sampling channels
No active antialiasing filter required
LNA and PGA with 45 dB gain range in 6 dB steps
Selectable equalizer
Flexible data port supports serial or parallel mode
Supports FSK mode for FMCW radar systems
On-chip 1.5 V reference
Internal oscillator/PLL input: 16 MHz to 54 MHz
High speed serial data interface
SPI control
2 general-purpose inputs/outputs
48-lead LFCSP_SS package
Temperature range: −40°C to +125°C
Single supply operation of 3.3 V
Qualified for automotive applications
APPLICATIONS
Automotive LSR systems
Data acquisition systems
GENERAL DESCRIPTION
The ADAR7251 is a 16-bit, 4-channel, simultaneous sampling
analog-to-digital converter (ADC) designed especially for
applications such as automotive LSR-FMCW or FSK-FMCW
radar systems. Each of the four channels contains a low noise
amplifier (LNA), a programmable gain amplifier (PGA), an
equalizer, a multibit Σ-Δ ADC, and a decimation filter.
The front-end circuitry is designed to allow direct connection
to an MMIC output with few external passive components. The
ADAR7251 eliminates the need for a high order antialiasing
filter, driver op amps, and external bipolar supplies. The
ADAR7251 also offers precise channel-to-channel drift
matching.
The ADAR7251 features an on-chip phase-locked loop (PLL)
that allows a range of clock frequencies for flexibility in the system.
The CONV_START input and DATA_READY output signals
synchronize the ADC with an external ramp for applications such
as FSK-FMCW radar.
The ADAR7251 supports serial and parallel interfaces at
programmable sample rates from 300 kSPS to 1.8 MSPS, as well
as easy connections to digital signal processors (DSPs) and
microcontroller units (MCUs) in the system.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADAR7251
SPECIFICATIONS
ANALOG CHANNEL
AVDDx = 3.3 V, DVDDx = 1.8 V, IOVDDx = 3.3 V, VREF = 1.5 V internal/external reference, fSAMPLE = 1.2 MSPS, TAMB = −40°C to +125°C,
unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min Typ Max Unit
DYNAMIC PERFORMANCE
Input Referred Noise Spectral Density
Frequency = 100 Hz
Gain = 9 dB
44.7 nV/√Hz
Gain = 15 dB
23.6 nV/√Hz
Gain = 21 dB
15 nV/√Hz
Gain = 27 dB
12 nV/√Hz
Gain = 33 dB
11.3 nV/√Hz
Gain = 39 dB
10.9 nV/√Hz
Gain = 45 dB
10.8 nV/√Hz
Frequency = 1 kHz
Gain = 9 dB
16 nV/√Hz
Gain = 15 dB
8.7 nV/√Hz
Gain = 21 dB
5.4 nV/√Hz
Gain = 27 dB
4.3 nV/√Hz
Gain = 33 dB
4 nV/√Hz
Gain = 39 dB
3.86 nV/√Hz
Gain = 45 dB
3.83 nV/√Hz
Frequency = 100 kHz
Gain = 9 dB
9.7 nV/√Hz
Gain = 15 dB
5.2 nV/√Hz
Gain = 21 dB
3.3 nV/√Hz
Gain = 27 dB
2.67 nV/√Hz
Gain = 33 dB
2.5 nV/√Hz
Gain = 39 dB
2.44 nV/√Hz
Gain = 45 dB
2.4 nV/√Hz
Equalizer Corner Frequency
Setting 1 EQ00
54 kHz
Setting 2 EQ01
45 kHz
Setting 3 EQ10
37 kHz
Setting 4 EQ11
32 kHz
Signal to Noise Ratio (SNR)
No input signal and reference to 0 dBFS 88
94
dB
Spurious-Free Dynamic Range (SFDR)
At −3 dBFS input, 100 kHz
68 82
dB
Total Harmonic Distortion Plus Noise (THD + N) At −3 dBFS input, 100 kHz
−80 −66 dB
At −1 dBFS input, 100 kHz
−77 −62 dB
Channel to Channel Crosstalk
At 50 kHz, −3 dBFS input
−94 −89
dB
Interchannel Gain Mismatch
−0.5 0
+0.5 dB
Interchannel Phase Mismatch
0.04 Degrees
DC Offset
−72 dBFS
Power Supply Rejection
Ripple = 100 mV rms on AVDDx at
1 kHz
65
dB
Rev. 0 | Page 5 of 72
5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
AVDDx to AGNDx, DGNDx
DVDDx to AGNDx, DGNDx
IOVDDx to AGNDx, DGNDx
AGNDx to DGNDx
Analog Input Voltage to AGNDx
Digital Input Voltage to DGNDx
Digital Output Voltage to DGNDx
Input Current to Any Pin Except Supplies
Operating Temperature Range (Ambient)
Junction Temperature Range
Storage Temperature Range
RoHS-Compliant Temperature Soldering
Reflow
Rating
−0.3 V to +3.63 V
−0.3 V to +1.98 V
−0.3 V to +3.63 V
−0.3 V to +0.3 V
−0.3 V to +3.63 V
−0.3 V to +3.63 V
−0.3 V to +3.63 V
±10 mA
−40°C to +125°C
−40°C to + 150°C
−65°C to +150°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ADAR7251
THERMAL RESISTANCE
θJA represents junction-to-ambient thermal resistance, and
θJC represents the junction-to-case thermal resistance. All
characteristics are for a standard JEDEC board per JESD51.
Table 8. Thermal Resistance
Package Type
θJA1 θJC1 Unit
48-Lead LFCSP_SS
25 1
°C/W
1JEDEC 2S2P standard board.
ESD CAUTION
Rev. 0 | Page 11 of 72
11 Page | ||
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