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PDF LTC6947IUFD Data sheet ( Hoja de datos )
| Número de pieza | LTC6947IUFD | |
| Descripción | Ultralow Noise 0.35GHz to 6GHz Fractional-N Synthesizer | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC6947
Ultralow Noise 0.35GHz to
6GHz Fractional-N Synthesizer
Features
Description
n Low Noise Fractional-N PLL
n No ∆Σ Modulator Spurs
n 18-Bit Fractional Denominator
n 350MHz to 6GHz VCO Input Range
n –226dBc/Hz Normalized In-Band Phase Noise Floor
n –274dBc/Hz Normalized In-Band 1/f Noise
n –157dBc/Hz Wideband Output Phase Noise Floor
n Excellent Integer Boundary Spurious Performance
n Output Divider (1 to 6, 50% Duty Cycle)
n Output Buffer Muting
n Charge Pump Supply from 3.15V to 5.25V
n Charge Pump Current from 1mA to 11.2mA
n Reference Input Frequency Up to 425MHz
n Fast Frequency Switching
n FracNWizard™ Software Design Tool Support
Applications
n Wireless Basestations (LTE, WiMAX, W-CDMA, PCS)
n Broadband Wireless Access
n Microwave Data Links
n Military and Secure Radio
n Test and Measurement
The LTC®6947 is a high performance, low noise, 6GHz
phase-locked loop (PLL), including a reference divider,
phase-frequency detector (PFD), ultralow noise charge
pump, fractional feedback divider, and VCO output divider.
The fractional divider uses an advanced, 4th order Δ∑
modulator which provides exceptionally low spurious
levels. This allows wide loop bandwidths, producing
extremely low integrated phase noise values.
The programmable VCO output divider, with a range of 1
through 6, extends the output frequency range. The dif-
ferential, low-noise output buffer has user-programmable
output power ranging from –4.3dBm to +4.5dBm, and may
be muted through either a digital input pin or software.
The ultralow noise charge pump contains selectable high
and low voltage clamps useful for VCO monitoring, and
also may be set to provide a V+/2 bias.
All device settings are controlled through a SPI-compatible
serial port.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
FracNWizard is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical Application
11GHz Source for Satellite Communications
0.1µF
0.1µF
10nF
3.3V
1µF
60.4Ω 5V
5V
0.01µF
3.3V
1µF
100MHz
51.1Ω
SPI BUS
3.3V
3.3V
REF+
STAT
CS
SCLK
SDI
SDO
LDO
VD+
LTC6947IUFD
GND
GND
GND
GND
GND
GND
VCO+
VCO–
4.99k
4.99k 0.1µF
0.01µF
+ 47µF
13V
+ LT1678IS8
OUT
–
10nF
0.1µF 5V
3.3nF
60.4Ω
220nF
100pF
fLO/2
100pF
VTUNE
MA-COM
MAOC-009266
47nF
0.1µF
75Ω
1nF
0.1µF
3.3V 68nH
3.3V 1µF
fLO = 10.2GHz TO 11.3GHz IN 381.4Hz STEPS
0.01µF
68nH 100pF
0.01µF
100pF
R = 2, fPFD = 50MHz
N = 102 TO 113
LBW = 33.6kHz
AUXILIARY OUTPUTS
fLO/2, /4, /6, /8, /10 OR /12
6947 TA01a
For more information www.linear.com/LTC6947
System Phase Noise,
fRF = 11.260GHz
–80
–90
–100
–110
–120
–130
–140
–150
RMS NOISE = 0.549°
RMS JITTER = 135fs
–160
fPFD = 50MHz
LOOP BW = 34kHz
–170 INTN = 0
–180 CPLE = 1
100 1k 10k 100k 1M 10M 100M
OFFSET FREQUENCY (Hz)
6946 TA01b
6947f
1
1 page  
LTC6947
E lectrical Characteristics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are
specified (Note 2). All voltages are with respect to GND.
at
TA
=
25°C.
VREF+
=
VD+
=
VRF+
=
VVCO+
=
3.3V,
VCP+
=
5V
unless
otherwise
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Phase Noise and Spurious
LMIN
LNORM(INT)
Output Phase Noise Floor (Note 5)
Integer Normalized In-Band Phase Noise
Floor
RFO[1:0] = 3, OD[2:0] = 1, fRF = 6GHz
RFO[1:0] = 3, OD[2:0] = 2, fRF = 3GHz
RFO[1:0] = 3, OD[2:0] = 3, fRF = 2GHz
RFO[1:0] = 3, OD[2:0] = 4, fRF = 1.5GHz
RFO[1:0] = 3, OD[2:0] = 5, fRF = 1.2GHz
RFO[1:0] = 3, OD[2:0] = 6, fRF = 1.0GHz
INTN = 1, ICP = 5.6mA (Notes 6, 7, 9)
–155 dBc/Hz
–155 dBc/Hz
–156 dBc/Hz
–156 dBc/Hz
–157 dBc/Hz
–158 dBc/Hz
–226 dBc/Hz
LNORM(FRAC)
Fractional Normalized In-Band Phase Noise
Floor
INTN =
(Notes
0,
6,
CPLE
7, 9)
=
1,
ICP
=
5.6mA
–225 dBc/Hz
L1/f
Normalized In-Band 1/f Phase Noise
ICP = 11.2mA (Notes 6, 10)
In-Band Phase Noise Floor
Fractional Mode, CPLE = 1
(Notes 4, 6, 7, 10, 11)
–274 dBc/Hz
–109 dBc/Hz
Integrated Phase Noise from 100Hz to
40MHz
Spurious
Fractional Mode, CPLE = 1 (Notes 4, 7, 11)
F(Nraoctteiosn4a,l7M, o1d1e, ,1f2O)FFSET = fPFD, PLL Locked
0.076
–97
°RMS
dBc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6947I is guaranteed to meet specified performance limits
over the full operating junction temperature range of –40°C to 105°C.
Note 3: For 0.9V < V(CP) < (VCP+ – 0.9V).
Note 4: VCO is Crystek CVCO55C-2328-2536.
Note 5: fVCO = 6GHz, fOFFSET = 40MHz.
Note 6: Measured inside the loop bandwidth with the loop locked.
Note 7: Reference frequency supplied by Wenzel 501-04516, fREF =
100MHz, PREF = 10dBm.
Note 8: Reference frequency supplied by Wenzel 500-23571, fREF =
61.44MHz, PREF = 10dBm.
Note 9: Output phase noise floor is calculated from normalized phase
noise floor by LOUT = LNORM + 10log10 (fPFD) + 20log10 (fRF/fPFD).
Note 10: Output 1/f noise is calculated from normalized 1/f phase noise by
LOUT(1/f) = L1/f + 20log10 (fRF) – 10log10 (fOFFSET).
Note 11: ICP = 5.6mA, fPFD = 50MHz, FILT[1:0] = 0, Loop BW = 31kHz;
fRF = 2415MHz, fVCO = 2415MHz.
Note 12: Measured using DC1846.
Note 13: VCO is RFMD UMX-918-D16-G.
For more information www.linear.com/LTC6947
6947f
5
5 Page 
LTC6947
Operation
The LTC6947 is a high performance fractional-N PLL,
and, combined with an external high performance VCO,
can produce low noise LO signals up to 6GHz. The output
frequency range may be further extended by utilizing the
output divider. The device is able to achieve superior inte-
grated phase noise by the combination of its extremely low
in-band phase noise performance and the wide bandwidth
allowed by its low spurious products.
The fractional-N feedback divider uses an advanced Δ∑
modulator, resulting in virtually no discrete modulator
spurious tones. The modulator may be disabled if integer-N
feedback is required.
Reference Input Buffer
The PLL’s reference frequency is applied differentially on
pins REF+ and REF–. These high impedance inputs are
self-biased and must be AC-coupled with 1µF capacitors
(see Figure 1 for a simplified schematic). Alternatively, the
inputs may be used single-ended by applying the refer-
ence frequency at REF+ and bypassing REF– to GND with
a 1µF capacitor. If the single-ended signal is greater than
2.7VP-P, then use a 47pF capacitor for the GND bypass.
A high quality signal must be applied to the REF± inputs
BIAS
1.9V
1 REF+
4.2k
VREF+
4.2k
VREF+
LOWPASS
FILT[1:0]
28 REF–
6947 F01
BST
Figure 1. Simplified REF Interface Schematic
as they provide the frequency reference to the entire PLL.
To achieve the part’s in-band phase noise performance,
apply a CW signal of at least 6dBm into 50Ω, or a square
wave of at least 0.5VP-P with slew rate of at least 40V/µs.
Additional options are available through serial port register
h0B to further refine the application. Bits FILT[1:0] control
the reference input buffer’s lowpass filter, and should be
set based upon fREF to limit the reference’s wideband
noise. The FILT[1:0] bits must be set correctly to reach the
LNORM normalized in-band phase noise floor. See Table 1
for recommended settings.
Table 1. FILT[1:0] Programming
FILT[1:0]
3
2
1
0
fREF
<20MHz
NA
20MHz to 50MHz
>50MHz
The BST bit should be set based upon the input signal level
to prevent the reference input buffer from saturating. See
Table 2 for recommended settings and the Applications
Information section for programming examples.
Table 2. BST Programming
BST
1
0
VREF
<2VP-P
≥2VP-P
Reference (R) Divider
A 5-bit divider, R_DIV, is used to reduce the frequency
seen at the PFD. Its divide ratio R may be set to any inte-
ger from 1 to 31, inclusive. Use the RD[4:0] bits found in
registers h06 to directly program the R divide ratio. See
the Applications Information section for the relationship
between R and the fREF, fPFD, fVCO, and fRF frequencies.
Phase/Frequency Detector (PFD)
The phase/frequency detector (PFD), in conjunction with
the charge pump, produces source and sink current pulses
proportional to the phase difference between the outputs
of the R and N dividers. This action provides the necessary
feedback to phase-lock the loop, forcing a phase align-
ment at the PFD’s inputs. The PFD may be disabled with
the CPRST bit which prevents UP and DOWN pulses from
being produced. See Figure 2 for a simplified schematic
of the PFD.
For more information www.linear.com/LTC6947
6947f
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC6947IUFD.PDF ] | |
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