PDF MT29C4G96MAZAPCJG-5IT Data sheet ( Hoja de datos )

Número de pieza	MT29C4G96MAZAPCJG-5IT
Descripción	NAND Flash and Mobile LPDDR
Fabricantes	Micron Technology
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Micron Confidential and Proprietary Preliminary‡ 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features NAND Flash and Mobile LPDDR 168-Ball Package-on-Package (PoP) MCP Combination Memory (TI OMAP™) MT29C4G48MAYAPAKQ-5 IT, MT29C4G48MAZAPAKQ-5 IT, MT29C4G48MAZAPAKQ-6 IT, MT29C4G96MAZAPCJG-5 IT, MT29C4G96MAZAPCJG-6 IT, MT29C8G96MAZAPDJV-5 IT, MT29C8G96MAZAPDJV-6 IT Features • Micron® NAND Flash and LPDDR components • RoHS-compliant, “green” package • Separate NAND Flash and LPDDR interfaces • Space-saving multichip package/package-on-package combination • Low-voltage operation (1.70–1.95V) • Industrial temperature range: –40°C to +85°C NAND Flash-Specific Features Organization • Page size – x8: 2112 bytes (2048 + 64 bytes) – x16: 1056 words (1024 + 32 words) • Block size: 64 pages (128K + 4K bytes) Mobile LPDDR-Specific Features • No external voltage reference required • No minimum clock rate requirement • 1.8V LVCMOS-compatible inputs • Programmable burst lengths • Partial-array self refresh (PASR) • Deep power-down (DPD) mode • Selectable output drive strength • STATUS REGISTER READ (SRR) supported1 Notes: 1. Contact factory for remapped SRR output. 2. For physical part markings, see Part Number- ing Information (page 2). Figure 1: PoP Block Diagram NAND Flash Power NAND Flash Device LPDRAM Power LPDRAM Device NAND Flash Interface LPDRAM Interface PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. F 03/10 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. 1 page Micron Confidential and Proprietary Preliminary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Standard Mode Register ................................................................................................................................. 171 Burst Length ............................................................................................................................................. 171 Burst Type ................................................................................................................................................ 172 CAS Latency ............................................................................................................................................. 173 Operating Mode ........................................................................................................................................ 174 Extended Mode Register ................................................................................................................................ 175 Temperature-Compensated Self Refresh ................................................................................................... 175 Partial-Array Self Refresh .......................................................................................................................... 176 Output Drive Strength ............................................................................................................................... 176 Status Read Register ...................................................................................................................................... 177 Bank/Row Activation ..................................................................................................................................... 179 READ Operation ............................................................................................................................................ 180 WRITE Operation .......................................................................................................................................... 191 PRECHARGE Operation ................................................................................................................................. 203 Auto Precharge .............................................................................................................................................. 203 Concurrent Auto Precharge ....................................................................................................................... 204 AUTO REFRESH Operation ............................................................................................................................ 209 SELF REFRESH Operation ............................................................................................................................. 210 Power-Down ................................................................................................................................................. 211 Deep Power-Down ................................................................................................................................... 213 Clock Change Frequency ............................................................................................................................... 215 Revision History ............................................................................................................................................ 216 Rev. F, Preliminary – 03/10 ........................................................................................................................ 216 Rev. E, Preliminary – 02/10 ........................................................................................................................ 216 Rev. D, Preliminary – 01/10 ........................................................................................................................ 216 Rev. C, Preliminary – 12/09 ........................................................................................................................ 216 Rev. B, Preliminary – 10/09 ........................................................................................................................ 216 Rev. A, Preliminary – 7/09 .......................................................................................................................... 217 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. F 03/10 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 5 Page Micron Confidential and Proprietary Preliminary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP MCP General Description MCP General Description Micron package-on-package (PoP) MCP products combine NAND Flash and Mobile LPDRAM devices in a single MCP. These products target mobile applications with low- power, high-performance, and minimal package-footprint design requirements. The NAND Flash and Mobile LPDRAM devices are also members of the Micron discrete mem- ory products portfolio. The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no shared address, control, data, or power balls). This bus architecture supports an op- timized interface to processors with separate NAND Flash and Mobile LPDRAM buses. The NAND Flash and Mobile LPDRAM devices have separate core power connections and share a common ground (that is, VSS is tied together on the two devices). The bus architecture of this device also supports separate NAND Flash and Mobile LPDRAM functionality without concern for device interaction. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. F 03/10 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 11 Page

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