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PDF SST25VF032B Data sheet ( Hoja de datos )
| Número de pieza | SST25VF032B | |
| Descripción | 32 Mbit SPI Serial Flash | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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A Microchip Technology Company
32 Mbit SPI Serial Flash
SST25VF032B
Data Sheet
SST 25 series Serial Flash family features a four-wire, SPI-compatible interface
that allows for a low pin-count package which occupies less board space and
ultimately lowers total system costs. The SST25VF032B devices are enhanced
with improved operating frequency which lowers power consumption.
SST25VF032B SPI serial flash memories are manufactured with SST's proprie-
tary, high-performance CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches.
Features
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– Upt o8 0M Hz
• Superior Reliability
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Auto AddressIncrement(AAI) Word Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (200 mils)
– 8-contact WSON (5X6m m)
• All devices are RoHS compliant
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25071A
http://www.Datasheet4U.com
12/11
1 page  
A Microchip Technology Company
32 Mbit SPI Serial Flash
SST25VF032B
Memory Organization
Data Sheet
The SST25VF032B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable blocks.
Device Operation
The SST25VF032B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF032B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
SCK MODE 0
MODE 3
MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON T CARE
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1327 F04.0
Figure 3: SPI Protocol
©2011 Silicon Storage Technology, Inc.
5
DS25071A
12/11
5 Page 
A Microchip Technology Company
32 Mbit SPI Serial Flash
SST25VF032B
High-Speed-Read (80 MHz)
Data Sheet
The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the
duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will automatically increment until the highest memory
address is reached. Once the highest memory address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space. For example, once the data from address
location 3FFFFFH has been read, the next output will be from address location 000000H.
CE#
MODE 3
SCK MODE 0
012 345 6 78
15 16
23 24 31 32 39 40
47 48
55 56 63 64 71 72
78
SI 0B ADD. ADD. ADD.
SO HIGH IMPEDANCE
Figure 6: High-Speed-Read Sequence
X
N
DOUT
MSB
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
1327 F07.1
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait TBP for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
CE#
SCK
MODE 3
MODE 0
012 345 6 78
15 16
23 24 31 32
39
SI 02
SO
Figure 7: Byte-Program Sequence
ADD.
ADD.
ADD.
DIN
MSB LSB
HIGH IMPEDANCE
1327 F08.0
©2011 Silicon Storage Technology, Inc.
11
DS25071A
12/11
11 Page | ||
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| PDF Descargar | [ Datasheet SST25VF032B.PDF ] | |
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