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PDF CS61310 Data sheet ( Hoja de datos )
| Número de pieza | CS61310 | |
| Descripción | T1 Line Interface Unit | |
| Fabricantes | Cirrus Logic | |
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CS61310
T1 Line Interface Unit
Features
Provides T1 line interface
No crystal needed for jitter attenuation
Greater than 14 dB of transmit return loss
Meets AT&T 62411 jitter tolerance and
attenuation requirements
Meets ANSI T1.231B requirements for LOS and
AIS
AWG for user programmable pulse shapes
TX driver high impedance / low power control
Generation and detection of loop up / loop down
signaling
Selectable unipolar or bipolar I/O
Compliant with:
— American National Standards (ANSI): T1.102, T1.105,
T1.403, T1.408, and T1.231
— FCC Rules and Regulations: Part 68 and Part 15
— AT&T Publication 62411
— TR-NET-00499
Description
The CS61310 is a T1 primary rate line interface unit. It
combines the complete analog transmit-and-receive cir-
cuitry for a single, full-duplex interface at T1 rates. The
device is pin- and function-compatible with the Level
One LXT310.
Enhanced functionality is available through an extended
register set, allowing custom pulse shape generation as
well as generation and detection of loop up and loop
down codes. The CS61310 features crystal-less jitter
attenuation.
ORDERING INFORMATION
CS61310-IL
28-pin PLCC
T CLK
TDATA/T POS
UBS/TNEG
JASEL
E
2N
C
3O
4
D
E
R
11
JITTER
ATTEN
REMOTE
LOOPBACK
LOCAL
LOOPBACK
(DIGITAL)
RCLK
RDATA/RPOS
BP V/ RNEG
D
8E
7
C
O
6
D
E
R
JITTER
ATTEN
TRANSMIT
TIMING &
CONTROL
PULSE
SHAPING
CIRCUITRY
ROM / RAM
LINE DRIVERS
TAOS Enable
LBO Select
SERIAL
PORT
REGISTERS & CONTROL LOGIC
LOS/
NLOOP
Clear
T IMING
& DATA
RECOVERY
LLOOP
Enable
EQUALIZER
CONTROL
SLICERS
& PEAK
DETECT
NOISE &
CROSSTALK
FILTERS
LOCAL
LOOPBACK
(ANALOG)
MAGNITUDE
EQUALIZER
AGC
13
TTIP
16
TRING
28
CLKE/TAOS
26
CS/RLOOP
27
SCLK/LLOOP
24
SDI/LBO1
25
SDO/LBO2
18
LATN
19
RTIP
20
RRING
INT /NLOOP
LOS
23
12
INBAND
NLOOP
& LOS
PROCESSOR
RECEIVE
CLOCK
GENERATOR
9
XTALIN
10
XTALOUT
1
MCLK
5 21 22 14 15
MODE RV+ RGND TGND TV+
Final Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
This document contains advanced information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS440F1
FEB ‘03
1
Free Datasheet http://www.datasheet4u.com/
1 page  
CS61310
ANALOG CHARACTERISTICS
(TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%; GND = 0 V)
Parameter
Min Typ Max Units
Transmitter
AMI Output Pulse Amplitudes
(Note 8)
T1, (FCC Part 68) (Note 9)
T1, DSX-1 (Note 10)
External Equalizer Pulse Amplitude
Transmitter Output Impedance
Transformer turns ratio = 1:2
(Note 12)
Transformer turns ratio = 1:1.5
FCC
DSX1
External Equalizer
Jitter Added by the Transmitter
(Notes 11,12)
10 Hz - 8 kHz
8 kHz - 40 kHz
10 Hz - 40 kHz
Broad Band
Power in 2 kHz band about 772 kHz
(Notes 8, 12)
Power in 2 kHz band about 1.544 MHz
(Notes 8, 12)
(referenced to power in 2 kHz band at 772 kHz)
Positive to Negative Pulse Imbalance
(Notes 8, 12)
Transmitter Short Circuit Current
(Notes 8, 13)
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0 dB = 3.0 V)
Loss of Signal Threshold
Data Decision Threshold (Notes 12,14)
T1, DSX-1
T1, (FCC Part 68)
Allowable Consecutive Zeros before LOS
Receiver Input Jitter Tolerance(Note 16) T1:10 kHz - 100 kHz
(Note 12) 1 Hz
2.7
2.4
4.8
-
-
-
-
12.6
-29
-
-
-
-40
30
-
160
0.4
138
3.0
3.0
5.6
1.5
44
44
44
0.015
0.015
0.015
0.020
15
-38
0.2
-
20k
-
-
-42
50
50
175
-
-
3.3 V
3.6 V
V
Ω
Ω
Ω
Ω
-
-
-
-
17.9
-
UI
UI
UI
UI
dBm
dB
0.5 dB
50 mA RMS
-Ω
- dB
- mV
- dB
% of peak
% of peak
190 bits
- UI
- UI
Notes: 8. Using a 0.47 µF capacitor in series with the primary of a transformer recommended in the Applications
Section.
9. Pulse amplitude measured at the secondary side of the transformer across a 100 Ω load for line length
setting LEN2/1/0 = 0/1/0.
10. Pulse amplitude measured at the DSX-1 Cross-Connect for all line length settings from LEN2/1/0 =
0/1/1 to LEN2/1/0 = 1/1/1.
11. Assuming that jitter free clock is input to TCLK.
12. Not production tested. Parameters guaranteed by design and characterization.
13. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer
during the transmission of an all ones data pattern.
14. Data decision threshold established after the receiver equalizer filters pulse overshoot and undershoot.
15. Jitter tolerance for 0 dB input signal level. Jitter tolerance increases at lower frequencies. See Figure 7.
16. See Receiver Jitter Tolerance Plot, Figure 7.
DS440F1 FEB ‘03
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
CS61310
2.5 Jitter Attenuator
Jitter attenuation can be implemented in either the
transmit (JASEL low) or receive (JASEL high)
paths, or it can be eliminated from the circuit by
setting the XTALIN pin high. The jitter attenuator
on the CS61310 does not require a crystal. It is ac-
tivated when XTALIN is either connected to ground
or left open; connecting to ground is the preferred
method.
The jitter attenuator corner frequency is set at
4 Hz, with attenuation increasing at a 20 dB per
decade rate above 4 Hz. A typical jitter attenuation
graph is shown in Figure 8.
2.6 Receiver Line Attenuation Indication
The LATN pin outputs a coded signal that repre-
sents the signal level at the input of the receiver. As
shown in Figure 9, the LATN output is measured
against RCLK to provide the signal level in 7.5 dB
increments. In host mode, the receive input signal
level can be read from the Equalizer Gain register,
address 0x12, to greater resolution, dividing the in-
put range into 20 steps of 2 dB increments.
0
M inimum A ttenuation Lim it
10
20 62411 Requirem ents
30
40 Maximum
A tte n u a tio n
50 Lim it
60
M easured Perform ance
1 10 100 1 k 10 k
Frequency in Hz
Figure 8. Typical Jitter Transfer Function
2.7 Receiver Loss of Signal
The receiver will indicate loss of signal by setting
the LOS pin high in hardware mode (CR1.0 = 1 in
host mode). LOS is active on power up, reset,
when receiver gain is maximized, upon receiving
175+/-15 consecutive zeros, or when the received
signal power falls below below the signal level,
“Loss of Signal Threshold” listed under Analog
Specifications. Received zeros are counted based
on recovered clock cycles. While in the LOS state,
received data on RPOS/RNEG (RDATA in unipolar
mode) equals 0 (squelched). The device complies
with ANSI T1.231-1993 criteria to exit the LOS
condition: 12.5% ones density for 175+/-75 bit pe-
riods with no more than 100 consecutive zeros.
While LOS is active, RCLK depends on MCLK and
the jitter attenuator. If the jitter attenuator is in the
transmit path or not used, RCLK is referenced to
MCLK, if provided, or the crystal oscillator other-
wise. If the jitter attenuator is in the receive path,
the jitter attenuator will hold the average incoming
data frequency prior to LOS. The recovered clock
remains at a 50% duty cycle. The RPOS (RDATA)
and RNEG pins are forced low during LOS.
Timing is recovered by a phase selector which se-
lects one of the phases from the internal synchro-
nization clock (one of three clocks, 120 degrees
apart in phase, at 16X of the data rate). Since the
selection is made between a limited set of phases,
the Digital Timing Recovery process has a small
phase error built into the sampling process. By
choosing from 48 possible sampling phases, the
CS61310 reduces the sampling error to a mini-
mum.
RCLK
LATN
1 2 3 45
LATN = 1 R C LK, 7.5 dB of Attenuation
LATN = 2 R C LK , 15 dB of Attenuation
LATN = 3 R C LK , 22.5 dB of A ttenuation
LA TN = 4 RC LK , 0 dB of Attenuation
Figure 9. LATN Pulse Width encoding
DS440F1 FEB ‘03
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS61310.PDF ] | |
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