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PDF LPC4320 Data sheet ( Hoja de datos )
| Número de pieza | LPC4320 | |
| Descripción | (LPC4310 - LPC4350) 32-bit ARM Cortex-M4/M0 MCU | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet;
two High-speed USBs; advanced configurable peripherals
Rev. 3.1 — 5 January 2012
Objective data sheet
1. General description
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embedded
applications which include an ARM Cortex-M0 coprocessor, up to 264 kB of SRAM,
advanced configurable peripherals such as the State Configurable Timer (SCT) and the
Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet,
LCD, an external memory controller, and multiple digital and analog peripherals. The
LPC4350/30/20/10 operate at CPU frequencies of up to 204 MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard architecture with separate local instruction and data buses as well as a third bus
for peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,
designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz
performance with a simple instruction set and reduced code size.
Remark: This data sheet describes the Rev ‘A’ versions of parts LPC4350/30/20/10.
Compared to previous versions, the following updates apply:
• Operating frequency increased to 204 MHz.
• C_CAN1 added.
• Pin multiplexing increased to up to 9 levels.
• GPIO block updated.
• Pads updated.
2. Features and benefits
Cortex-M4 Processor core
ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit.
Non-maskable Interrupt (NMI) input.
Free Datasheet http://www.datasheet4u.com/
1 page  
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
4. Ordering information
Table 1. Ordering information
Type number Package
Name
Description
LPC4350FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
LPC4350FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls
LPC4350FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC4330FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
LPC4330FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls
LPC4330FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm
LPC4330FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC4320FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm
LPC4320FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC4320FBD100 LQFP100 Plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm
LPC4310FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm
LPC4310FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
Version
SOT740-2
SOT570-3
SOT459-1
SOT740-2
SOT570-3
SOT926-1
SOT486-1
SOT926-1
SOT486-1
SOT407-1
SOT926-1
SOT486-1
4.1 Ordering options
Table 2. Ordering options
Type number
Total LCD Ethernet USB0 USB1 ADC
PWM QEI GPIO Package
SRAM
(Host, (Host, channels
Device, Device)/
OTG) ULPI
interface
LPC4350FET256 264 kB yes yes
yes yes/yes 8
yes yes 164 LBGA256
LPC4350FET180 264 kB yes yes
yes yes/yes 8
yes yes 118 TFBGA180
LPC4350FBD208 264 kB yes yes
yes yes/yes 8
yes yes 142 LQFP208
LPC4330FET256 264 kB no yes
yes yes/yes 8
yes yes 164 LBGA256
LPC4330FET180 264 kB no yes
yes yes/yes 8
yes yes 118 TFBGA180
LPC4330FET100 264 kB no yes
yes yes/no 4
no no 49 TFBGA100
LPC4330FBD144 264 kB no yes
yes yes/no 8
yes no 83 LQFP144
LPC4320FET100 200 kB no no
yes no
4
no no 49 TFBGA100
LPC4320FBD144 200 kB no no
yes no
8
yes no 83 LQFP144
LPC4320FBD100 200 kB no no
yes no
5
no no 49 LQFP100
LPC4310FET100 168 kB no no
no no
4
no no 49 TFBGA100
LPC4310FBD144 168 kB no no
no no
8
yes no 83 LQFP144
LPC4350_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 5 January 2012
© NXP B.V. 2012. All rights reserved.
5 of 149
Free Datasheet http://www.datasheet4u.com/
5 Page 
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
Description
P1_5
P1_6
P1_7
R5 x J4 65 48 33 [3] I; PU I/O GPIO1[8] — General purpose digital input/output pin.
O CTOUT_10 — SCT output 10. Match output 2 of
timer 2.
- R — Function reserved.
O EMC_CS0 — LOW active Chip Select 0 signal.
O USB0_PWR_FAULT — Port power fault signal
indicating overcurrent condition; this signal monitors
over-current on the USB bus (external circuitry
required to detect over-current condition).
I/O SSP1_SSEL — Slave Select for SSP1.
I/O SGPIO15 — General purpose digital input/output pin.
O SD_POW — SD/MMC power monitor output.
T4 x K4 67 49 34 [3] I; PU I/O GPIO1[9] — General purpose digital input/output pin.
I CTIN_5 — SCT input 5. Capture input 2 of timer 2.
- R — Function reserved.
O EMC_WE — LOW active Write Enable signal.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO14 — General purpose digital input/output pin.
I/O SD_CMD — SD/MMC command signal.
T5 x G4 69 50 35 [3] I; PU I/O GPIO1[0] — General purpose digital input/output pin.
I U1_DSR — Data Set Ready input for UART1.
O CTOUT_13 — SCT output 13. Match output 1 of
timer 3.
I/O EMC_D0 — External memory data line 0.
O USB0_PPWR — VBUS drive signal (towards external
charge pump or power management unit); indicates
that VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch
at reset. This signal has opposite polarity compared
to the USB_PPWR used on other NXP LPC parts.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
LPC4350_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 5 January 2012
© NXP B.V. 2012. All rights reserved.
11 of 149
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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| PDF Descargar | [ Datasheet LPC4320.PDF ] | |
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