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PDF RT3PE600L Data sheet ( Hoja de datos )
| Número de pieza | RT3PE600L | |
| Descripción | Radiation-Tolerant ProASIC3 Low-Power Space-Flight Flash FPGAs | |
| Fabricantes | ACTEL | |
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Radiation-Tolerant ProASIC3 Low-Power Space-
Flight Flash FPGAs
with Flash*Freeze Technology
®
Features and Benefits
MIL-STD-883 Class B Qualified Packaging
• Ceramic Column Grid Array with Six Sigma Copper-
Wrapped Lead-Tin Columns
• Land Grid Array
Low Power
• Dramatic Reduction in Dynamic and Static Power
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low
Power
• Low Power Consumption in Flash*Freeze Mode Enables
Instantaneous Entry To / Exit From Low-Power
Flash*Freeze Mode
• Supports Single-Voltage System Operation
• Low-Impedance Switches
Radiation Tolerant
• 15 krad Total Ionizing Dose (TID)
• Wafer-Lot-Specific TID Reports
High Capacity
• 600 k to 3 M System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced and Pro (Professional) I/Os
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage
Operation
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (RT3PE3000L only)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay (RT3PE3000L only)
• Schmitt Trigger Option on Single-Ended Inputs
(RT3PE3000L)
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the Radiation-Tolerant
ProASIC®3 Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, All with Integrated PLL (RT ProASIC3)
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
High Performance
• 350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems)
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4,
×9, and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Blocks with Synchronous Operation:
– 250 MHz: For 1.2 V Systems
– 350 MHz: For 1.5 V Systems
Table I-1 • Radiation-Tolerant (RT) ProASIC3 Low-Power Space-Flight FPGAs
RT ProASIC3 Devices
RT3PE600L
RT3PE3000L
System Gates
600 k
3M
VersaTiles (D-flip-flops)
13,824
75,264
RAM kbits (1,024 bits)
108
504
4,608-Bit Blocks 24 112
FlashROM Bits
1k 1k
Secure (AES) ISP
Yes
Yes
Integrated PLL in CCCs
6
6
VersaNet Globals
18
18
I/O Banks
88
Maximum User I/Os
270
620
Package Pins
CCGA/LGA
CG/LG484
CG/LG484, CG/LG896
September 2008
© 2008 Actel Corporation
I
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1 – Radiation-Tolerant ProASIC3 Low-Power Space-
Flight FPGA Overview
General Description
The radiation-tolerant (RT) ProASIC3 family of Actel flash FPGAs dramatically reduces dynamic
power consumption by 40% and static power by 50%. These power savings are coupled with
performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability,
and advanced features. The RT ProASIC3 FPGA is based on Actel's ProASIC3EL family of low-power
FPGAs.
Actel's proven Flash*Freeze technology enables RT ProASIC3 device users to shut off dynamic
power instantaneously and switch the device to static mode without the need to switch off clocks
or power supplies, and retaining internal states of the device. This greatly simplifies power
management. In addition, optimized software tools using power-driven layout provide instant
push-button power reduction.
Nonvolatile flash technology gives RT ProASIC3 devices the advantage of being a secure, low-
power, single-chip solution that is live at power-up (LAPU). RT ProASIC3 devices offer dramatic
dynamic power savings, giving FPGA users flexibility to combine low power with high performance.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
RT ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). RT ProASIC3
devices support devices from 600 k system gates to 3 million system gates with up to 504 kbits of
true dual-port SRAM and 620 user I/Os.
Flash*Freeze Technology
RT ProASIC3 devices offer Actel's proven Flash*Freeze technology, which allows instantaneous
switching from an active state to a static state. When Flash*Freeze mode is activated, RT ProASIC3
devices enter a static state while retaining the contents of registers and SRAM. Power is conserved
without the need for additional external components to turn off I/Os or clocks. Flash*Freeze
technology is combined with in-system programmability, which enables users to quickly and easily
upgrade and update their designs in the final stages of manufacturing or in the field. The ability of
RT ProASIC3 devices to support a 1.2 V core voltage allows for an even greater reduction in power
consumption, which enables low total system power.
When the RT ProASIC3 device enters Flash*Freeze mode, the device automatically shuts off the
clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes
and data is retained.
The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage
solution, make RT ProASIC3 devices suitable for low-power data transfer and manipulation in
military-temperature applications where available power may be limited (e.g., in battery-powered
equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced cooling).
Flash Advantages
Low Power
The RT ProASIC3 family of Actel flash-based FPGAs provides a low-power advantage, and when
coupled with high performance, enables designers to make power-smart choices using a single-
chip, reprogrammable, and live-at-power-up device.
RT ProASIC3 devices offer 40% dynamic power and 50% static power savings by reducing the core
operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero® Integrated
Design Environment (IDE) offers up to 30% additional power reduction. With Flash*Freeze
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Radiation-Tolerant ProASIC3 Device Family Overview
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheets are published before data
has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"
"Preliminary," and "Production." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains
general product information. This document gives an overview of specific device and family
information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or
speed grades. This information can be used as estimates, but not for production. This label only
applies to the DC and Switching Characteristics chapter of the datasheet and will only be used
when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The
information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations
(EAR). They could require an approved export license prior to export from the United States. An
export includes release of product or disclosure of technology to a foreign national inside or
outside the United States.
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status document may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the
responsibility of each customer to ensure the fitness of any Actel product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability
exclusions relating to life-support applications. A reliability report covering all of Actel’s products is
available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also
offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Actel sales office for additional reliability information.
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| Número de pieza | Descripción | Fabricantes |
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