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PDF TV5715 Data sheet ( Hoja de datos )

Número de pieza TV5715
Descripción TrueView 5715
Fabricantes Tvia 
Logotipo Tvia Logotipo



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No Preview Available ! TV5715 Hoja de datos, Descripción, Manual

TRUEVIEWTM 5715
INTRODUCTION
The TrueView5715 is a low pin count and low cost member
of the TrueViewfamily of advanced and highly integrated
Multimedia Display Processors providing the key features
needed to design the next generation progressive scan CRT
Televisions.
The TrueView 5715 offers a unique solution to support and
process video streams up to 1080I. It has a built-in de-
Interlacer, advanced scaler, and dithering which enables a
video source to stream through and be displayed without
compromising the video quality.
With the high quality video DACs, the video stream is
displayed through its de-interlaced RGB/YPbPr outputs.
The I2C host interface enables OEMs to select from many
different CPU’s in order to meet their system and technical
requirements.
OEMs can easily design a very low cost solution, while
minimizing their software development time by leveraging on
the TrueView 5715’s level of integration and software support.
The TrueView 5715 provides 3D motion adaptive de-
interlacing with diagonal detection. It performs high quality
line doubling and high-accuracy motion estimation. It
performs pixel- based motion estimation using two-field
buffers. The Video Deinterlacing Processor automatically
detects and can respond to noise thresholds (for improved
mode detection) and still images (for reduced signal
processing errors).
Additionally the TrueView 5715 includes an integrated OSD
generator.
SDRAM
MA MD MCLK
RESET
Reset
Logic
External Memory Interface
R/Cr/Y
B/Cb/UV
G/Y/YUV
HSIN
VSIN
CLKIN
XTALI
XTALO
Input
Formatter
De-Interlacer
3D
Time-
Space
Converter
CRYSTAL
OSC
PLL
Serial Host Interface
Video
Enhancement
OSD
GEN
16 Bit
Digital
Out
YUV
Matrix
Quad
DAC
R/V
B/U
G/Y
SVM
Tvia, Inc.
1 DS-5715-1.01

1 page




TV5715 pdf
TRUEVIEWTM 5715
Pin #
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
VR2
VR3
VR4
VR5
VR6
VR7
PVDD
PVSS
MD0
MD15
MD1
MD14
MD2
MD13
MD3
MD12
MD4
PVDD
PVSS
MD11
MD5
MD10
MD6
MD9
MD7
MD8
DQM#
PVDD
SDCLK
PVSS
WE#
RAS#
CAS#
FBCLK
BA
CS1#
VSS
VDD
CS0#
MA9
MA10
PVDD
PVSS
Pin Description
Video Red Input data2
Video Red Input data3
Video Red Input data4
Video Red Input data5
Video Red Input data6
Video Red Input data7
3.3V Digital Power
Digital GND
Memory Data Bus 0
Memory Data Bus 15
Memory Data Bus 1
Memory Data Bus 14
Memory Data Bus 2
Memory Data Bus 13
Memory Data Bus 3
Memory Data Bus 12
Memory Data Bus 4
3.3V I/O Power
I/O GND
Memory Data Bus 11
Memory Data Bus 5
Memory Data Bus 10
Memory Data Bus 6
Memory Data Bus 9
Memory Data Bus 7
Memory Data Bus 8
SDRAM data qualify signal
3.3V I/O Power
SDRAM clock
I/O GND
Write control for SDRAM
Row address strobe
Column address strobe
Feed back clock for memory controller
SDRAM bank select
Chip Selection 1
Core Power GND
3.3V Core Power
Chip Selection 0
Memory address bus 9
Memory address bus 10
3.3V I/O Power
I/O GND
Tvia, Inc.
6
I/O Note
I/O YCBCR data for 16-bit 4:2:2 mode.
I/O
I/O
I/O
I/O
I/O
P
G
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
G
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
P
O
G
O
O
O
I
O
O
G
P
O
I/O
I/O
P
G
DS-5715-1.01

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