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PDF CY8C20266A Data sheet ( Hoja de datos )
| Número de pieza | CY8C20266A | |
| Descripción | CapSense Applications | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8C20X36A/46A/66A/96A
CapSense® Applications
Features
■ 1.71V to 5.5V Operating Range
■ Low Power CapSense™ Block
❐ Configurable Capacitive Sensing Elements
❐ Supports Combination of CapSense Buttons, Sliders, Touch-
pads, Touch Screens, and Proximity Sensor
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running to 24 MHz
❐ Low Power at High Speed
❐ Interrupt Controller
❐ Temperature Range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ Three Program/Data Storage Size Options:
• CY8C20x36A: 8K Flash / 1K SRAM
• CY8C20x46A, CY8C20x96A: 16K Flash / 2K SRAM
• CY8C20x66A: 32K Flash / 2K SRAM
❐ 50,000 Flash Erase/Write Cycles
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ In-System Serial Programming (ISSP)
■ Full Speed USB
❐ Available on CY8C20646A, CY8C20666A, CY8C20x96A
only
❐ 12 Mbps USB 2.0 Compliant
❐ Eight Unidirectional Endpoints
❐ One Bidirectional Control Endpoint
❐ Dedicated 512 Byte Buffer
❐ Internally Regulated at 3.3V
■ Precision, Programmable Clocking
❐ Internal Main Oscillator: 6/12/24 MHz ± 5%
❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep Timers
❐ Precision 32 kHz Oscillator for Optional External Crystal
❐ 0.25% Accuracy for USB with No External Components
(CY8C20646A, CY8C20666A, CY8C20x96A only)
■ Programmable Pin Configurations
❐ Up to 36 GPIO (Depending on Package)
❐ Dual Mode GPIO: All GPIO Support Digital I/O and Analog
Input
❐ 25 mA Sink Current on All GPIO
❐ Pull up, High Z, Open Drain Modes on All GPIO
❐ CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:
www.Da• t2aS0hmeeAt4(Uat.c3o.0mV) Total Source Current on Port 0
• 20 mA (at 3.0V) Total Source Current on Port 1
❐ Selectable, Regulated Digital I/O on Port 1
❐ Configurable Input Threshold on Port 1
❐ Hot Swap Capability on all Port 1 GPIO
■ Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of I/O
❐ High PSRR Comparator
❐ Low Dropout Voltage Regulator for All Analog Resources
■ Additional System Resources
❐ I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No Clock Stretching Required (under most conditions)
• Implementation During Sleep Modes with Less Than
100 µA
• Hardware Address Validation
❐ SPI™ Master and Slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-Bit Timers
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ Integrated Supervisory Circuit
❐ 8-bit Delta-Sigma Analog-to-Digital Converter
❐ Two General Purpose High Speed, Low Power Analog Com-
parators
■ Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■ Package Options
❐ CY8C20x36A:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN
❐ CY8C20x46A:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
❐ CY8C20x96A:
• 24-Pin 4 x 4 x 0.6 mm QFN (with USB)
• 32-Pin 5 x 5 x 0.6 mm QFN (with USB)
❐ CY8C20x66A:
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
• 48-Pin SSOP
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54459 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 14, 2009
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CY8C20X36A/46A/66A/96A
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assem-
blers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC devices that match your system
requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over on-
chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
www.DataSheet4U.com
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 001-54459 Rev. **
Page 5 of 38
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CY8C20X36A/46A/66A/96A
32-Pin QFN
Table 5. Pin Definitions - CY8C20436A, CY8C20446A, CY8C20466A PSoC Device [2, 3]
Pin
No.
Type
Digital Analog
Name
Description
Figure 5. CY8C20436A, CY8C20446A, CY8C20466A
PSoC Device
1 IOH
I P0[1] Integrating input
2 I/O
I P2[7]
3 I/O
I P2[5] Crystal output (XOut)
4 I/O
5 I/O
6 I/O
7 I/O
8 IOHR
9 IOHR
10 IOHR
11 IOHR
I P2[3] Crystal input (XIn)
I P2[1]
AI, P0[1]
AI, P2[7]
1
2
24 P0[0], AI
23 P2[6], AI
I P3[3]
I P3[1]
I P1[7] I2C SCL, SPI SS
I P1[5] I2C SDA, SPI MISO
I P1[3] SPI CLK.
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
3
4
5
6
7
8
QFN
(Top View)
22
21
20
19
18
17
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
I P1[1] ISSP CLK[1], I2C SCL, SPI MOSI.
12 Power
13 IOHR
I
Vss Ground connection.
P1[0] ISSP DATA[1], I2C SDA., SPI CLK
14 IOHR
I P1[2]
15 IOHR
I P1[4] Optional external clock input
(EXTCLK)
16 IOHR
I P1[6]
17
Input
XRES Active high external reset with
internal pull down
18 I/O
I P3[0]
19 I/O
I
20 I/O
I
21 I/O
I
22 I/O
I
23 I/O
I
24 IOH
I
25 IOH
I
26 IOH
I
27 IOH
I
28 Power
29 IOH
I
30 IOH
I
31 IOH
I
32 Power
CP Power
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
Vss
Vss
Supply voltage
Integrating input
Ground connection
Center pad must be connected to
ground
wwwL.EDGaEtNaDSheAe=t4AUna.lcoogm, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-54459 Rev. **
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| PDF Descargar | [ Datasheet CY8C20266A.PDF ] | |
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