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PDF CY8C20046 Data sheet ( Hoja de datos )
| Número de pieza | CY8C20046 | |
| Descripción | CapSense Applications | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8C20x46, CY8C20x66
CapSense™ Applications
Features
■ Low Power CapSenseTM Block
❐ Configurable Capacitive Sensing Elements
❐ Supports Combination of CapSense Buttons, Sliders,
Touchpads, TouchScreens, and Proximity Sensors
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running to 24 MHz
❐ Low Power at High Speed
❐ Interrupt Controller
❐ 1.71V to 5.5V Operating Voltage
❐ Temperature Range: – 40°C to +85°C
■ Flexible On-Chip Memory
❐ Two Program Storage Size Options
• CY8C20x46: 16K Flash
• CY8C20x66: 32K Flash
❐ 50,000 Erase/Write Cycles
❐ 2048 Bytes SRAM Data Storage
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ In-System Serial Programming (ISSP)
■ Full-Speed USB (12 Maps)
❐ Eight Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 512 Byte Buffer
❐ Internal 3.3V Output Regulator
❐ Available on 48-Pin QFN and 48-Pin SSOP packages only
❐ Operating voltage with USB enabled:
• 3.15 to 3.45V when supply voltage is around 3.3V
• 4.35 to 5.25V when supply voltage is around 5.0V
■ Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■ Precision, Programmable Clocking
❐ Internal ± 5.0% 6/12/24 MHz Main Oscillator
❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep
❐ Optional External 32 kHz Crystal
www.Da❐ta0S.2h5e%et4AUc.ccuormacy for USB with No External Components
■ Programmable Pin Configurations
❐ 25 mA Sink Current on All GPIO
❐ Pull Up, High Z, Open Drain Drive Modes on All GPIO
❐ CMOS Drive Mode on Ports 0 and 1
❐ Up to 36 Analog Inputs on GPIO
❐ Configurable Inputs on All GPIO
❐ Selectable, Regulated Digital IO on Port 1
❐ Configurable Input Threshold for Port 1
❐ 3.0V, 20 mA Total Port 1 Source Current
❐ 5 mA Source Current Mode on Ports 0 and 1
❐ Hot-Swap Capability on all Port1 GPIO
■ Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of IO Combinations
❐ High PSRR Comparator
❐ Low Dropout Voltage Regulator for the Analog Array
■ Additional System Resources
❐ I2C™ Slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation Requires No Clock Stretching
• Implementation During Sleep Modes with
Less Than 100 µA
• Hardware Address Detection
❐ SPI™ Master and SPI Slave
• Configurable Between 46.9 kHz – 12 MHz
❐ Three 16-Bit Timers
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ Integrated Supervisory Circuit
■ Package Options
❐ 16-Pin 3x3 x 0.6 mm QFN
❐ 24-Pin 4x4 x 0.6 mm QFN
❐ 32-Pin 5x5 x 0.6 mm QFN
❐ 48-Pin 7x7 x 1.0 mm QFN (CY8C20x66 only)
❐ 48-Pin SSOP
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12696 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 13, 2008
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CY8C20x46, CY8C20x66
Development Tools
PSoC Designer™ is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assem-
blers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC Mixed-Signal Controllers that match
your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over on-
chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
www.DataSheet4U.com
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 001-12696 Rev. *C
Page 5 of 34
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CY8C20x46, CY8C20x66
48-Pin SSOP Part Pinout
Table 5. 48-Pin SSOP Part Pinout(2)
Name
Description
1 IOH IO
2 IOH IO
3 IOH IO
4 IOH IO
5 IO IO
6 IO IO
7 IO IO
8 IO IO
9
10
11 IO IO
12 IO IO
13
14 IO IO
15 IO IO
16 IO IO
17 IO IO
18
19
20 IOHR IO
21 IOHR IO
22 IOHR IO
23 IOHR IO
24
25 IOHR IO
26 IOHR IO
27 IOHR IO
28 IOHR IO
29
30
31
32
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
NC
P4[3]
P4[1]
NC
P3[7]
P3[5]
P3[3]
P3[1]
NC
NC
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[0]
P1[2]
P1[4]
P1[6]
NC
NC
NC
NC
XTAL Out
XTAL In
No connection
No connection
No connection
No connection
No connection
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
TC CLK(1), I2C SCL, SPI MOSI
Ground Pin
TC DATA(1), I2C SDA, SPI
CLK
EXT CLK
No connection
No connection
No connection
No connection
Figure 5. CY8C20546, CY8C20566-48-Pin SSOP PSoC Device
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
NC
P4[3]
P4[1]
NC
P3[7]
P3[5]
P3[3]
P3[1]
NC
NC
P1[7]
P1[5]
P1[3]
P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48 VDD
47 P0[6]
46 P0[4]
45 P0[2]
44 P0[0]
43 P2[6]
42 P2[4]
41 P2[2]
40 P2[0]
39 P3[6]
38 P3[4]
37 P3[2]
36 P3[0]
35 XRES
34 NC
33 NC
32 NC
31 NC
30 NC
29 NC
28 P1[6]
27 P1[4]
26 P1[2]
25 P1[0]
Name
Description
33 NC
34 NC
35 XRES
36 IO IO P3[0]
www3.7DatIOaSheetIO4U.coPm3[2]
38 IO IO P3[4]
39 IO IO P3[6]
40 IO IO P2[0]
No connection
No connection
Active high external reset with
internal pull down
41
42
43
44
45
46
47
48
IO IO
IO IO
IO IO
IOH IO
IOH IO
IOH IO
IOH IO
Power
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Power Pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
Document Number: 001-12696 Rev. *C
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| PDF Descargar | [ Datasheet CY8C20046.PDF ] | |
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