|
|
PDF CY7C0837AV Data sheet ( Hoja de datos )
| Número de pieza | CY7C0837AV | |
| Descripción | (CY7C08xxxV) FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C0837AV (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
|
No Preview Available !
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
FLEx18™ 3.3V 64K/128K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
Features
Functional Description
■ True Dual-Ported Memory Cells that Allow Simultaneous
Access of the Same Memory Location
■ Synchronous Pipelined Operation
■ Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices
■ Pipelined Output Mode Allows Fast Operation
■ 0.18 micron CMOS for Optimum Speed and Power
■ High Speed Clock to Data Access
■ 3.3V Low Power
❐ Active as Low as 225 mA (typ)
❐ Standby as Low as 55 mA (typ)
■ Mailbox Function for Message Passing
■ Global Master Reset
■ Separate Byte Enables on Both Ports
■ Commercial and Industrial Temperature Ranges
■ IEEE 1149.1 Compatible JTAG Boundary Scan
■ 144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
■ 120 TQFP (14 mm x 14 mm x 1.4 mm)
■ Pb-Free Packages Available
■ Counter Wrap Around Control
❐ Internal Mask Register Controls Counter Wrap Around
❐ Counter-Interrupt Flags to Indicate Wrap Around
❐ Memory Block Retransmit Operation
The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,
and 9 Mbit pipelined, synchronous, true dual port static RAMs
that are high speed, low power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location by
more than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal setup and hold
time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0833AV device in this family has limited features. See
Address Counter and Mask Register Operations [16] on page 6
for details.
■ Counter Readback on Address Lines
■ Mask Register Readback on Address Lines
■ Dual Chip Enables on Both Ports for Easy Depth Expansion
Table 1. Product Selection Guide
Density
Part Number
Maximum Speed (MHz)
Maximum Access Time -
Clock to Data (ns)
Typical Operating
Current (mA)
Package
512 Kbit
(32K x 18)
CY7C0837AV
167
4.0
225
144 FBGA
1 Mbit
(64K x 18)
CY7C0830AV
167
4.0
225
120 TQFP
144 FBGA
2 Mbit
(128K x 18)
CY7C0831AV
167
4.0
225
120 TQFP
144 FBGA
4 Mbit
(256K x 18)
CY7C0832AV CY7C0832BV [1]
167 133
4.0 4.4
9 Mbit
(512K x 18)
CY7C0833AV
133
4.7
225 225 270
120 TQFP
144 FBGA
120 TQFP
144 FBGA
Note
1. CY7C0832AV and CY7C0832BV are functionally identical.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06059 Rev. *S
www.DataSheet.in
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 03, 2009
[+] Feedback
1 page  
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Definitions
Left Port
A0L–A18L[2]
ADSL[8]
Right Port
A0R–A18R[2]
ADSR[8]
CE0L[8]
CE1L[7]
CLKL
CNTENL[8]
CE0R[8]
CE1R[7]
CLKR
CNTENR[8]
CNTRSTL[7]
CNTRSTR[7]
CNT/MSKL[7]
CNT/MSKR[7]
DQ0L–DQ17L
OEL
INTL
DQ0R–DQ17R
OER
INTR
CNTINTL[9]
CNTINTR[9]
R/WL
R/WR
B0L–B1L
B0R–B1R
MRST
TMS
TDI
TCK
TDO
VSS
VDD
Description
Address Inputs.
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Clock Signal. Maximum clock input rate is fMAX.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are
asserted LOW.
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations are used for message passing. INTL is asserted LOW when the
right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
deasserted HIGH when it reads the contents of its mailbox.
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all ‘1s.’
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corre-
sponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs.
Power Inputs.
Byte Select Operation
Control Pin
B0
B1
Effect
DQ0–8 Byte Control
DQ9–17 Byte Control
Document #: 38-06059 Rev. *S
www.DataSheet.in
Page 5 of 28
[+] Feedback
5 Page 
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 5. Scan Chain for 9 Mb Device
TDO
TDO
D2
TDI
TDO
D1
TDI
TDI
Table 4. Identification Register Definitions
Instruction Field
Revision Number (31:28)
Cypress Device ID (27:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Value
0h
C090h
C091h
C093h
C094h
034h
1
Description
Reserved for version number.
Defines Cypress part number for CY7C0832AV/CY7C0832BV
Defines Cypress part number for CY7C0831AV
Defines Cypress part number for CY7C0830AV
Defines Cypress part number for CY7C0837AV.
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Table 5. Scan Registers Sizes
Register Name
Instruction
Bypass
Identification
Boundary Scan
Bit Size
4
1
32
n[22]
Table 6. Instruction Identification Codes
Instruction
Code
Description
EXTEST
BYPASS
IDCODE
HIGHZ
CLAMP
SAMPLE/PRELOAD
NBSRST
RESERVED
0000
1111
1011
0111
0100
1000
1100
All other codes
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
Other combinations are reserved. Do not use other than the above.
Note
22. See details in the device BSDL file.
Document #: 38-06059 Rev. *S
www.DataSheet.in
Page 11 of 28
[+] Feedback
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CY7C0837AV.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C0837AV | (CY7C08xxxV) FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |