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PDF MAX19586 Data sheet ( Hoja de datos )
| Número de pieza | MAX19586 | |
| Descripción | 80Msps ADC with -82dBFS Noise Floor | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3758; Rev 0; 8/05
EVAALVUAAILTAIOBNLEKIT
High-Dynamic-Range, 16-Bit,www.DataSheet4U.com
80Msps ADC with -82dBFS Noise Floor
General Description
The MAX19586 is a 3.3V, high-speed, high-perfor-
mance analog-to-digital converter (ADC) featuring a
fully differential wideband track-and-hold (T/H) and a
16-bit converter core. The MAX19586 is optimized for
multichannel, multimode receivers, which require the
ADC to meet very stringent dynamic performance
requirements. With a -82dBFS noise floor, the
MAX19586 allows for the design of receivers with supe-
rior sensitivity requirements.
At 80Msps, the MAX19586 achieves a 79.2dB signal-to-
noise ratio (SNR) and an 84.3dBc/100dBc single-tone
spurious-free dynamic range (SFDR) performance
(SFDR1/SFDR2) at fIN = 70MHz. The MAX19586 is not
only optimized for excellent dynamic performance in
the 2nd Nyquist region, but also for high-IF input fre-
quencies. For instance, at 130MHz, the MAX19586
achieves an 82.5dBc SFDR and its SNR performance
stays flat (within 2.5dB) throughout the 4th Nyquist
region. This level of performance makes the part ideal
for high-performance digital receivers.
The MAX19586 operates from a 3.3V analog supply
voltage and a 1.8V digital voltage, features a 2.56VP-P
full-scale input range, and allows for a guaranteed sam-
pling speed of up to 80Msps. The input track-and-hold
stage operates with a 600MHz full-scale, full-power
bandwidth.
The MAX19586 features parallel, low-voltage CMOS-
compatible outputs in two’s-complement output format.
The MAX19586 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extend-
ed industrial (-40°C to +85°C) temperature range.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
High-Performance Instrumentation
Antenna Array Processing
Features
o 80Msps Minimum Sampling Rate
o -82dBFS Noise Floor
o Excellent Dynamic Performance
80dB/79.2dB SNR at fIN = 10MHz/70MHz
and -2dBFS
96dBc/102dBc Single-Tone SFDR1/
SFDR2 at fIN = 10MHz
84.3dBc/100dBc Single-Tone SFDR1/
SFDR2 at fIN = 70MHz
o Less than 0.1ps Sampling Jitter
o 1.1W Power Dissipation
o 2.56VP-P Fully Differential Analog Input Voltage
Range
o CMOS-Compatible Two’s-Complement Data
Output
o Separate Data Valid Clock and Over-Range
Outputs
o Flexible Input Clock Buffer
o 3.3V Analog Power Supply; 1.8V Digital Output
Supply
o Small 8mm x 8mm x 0.8mm 56-Pin Thin QFN
Package
o EV Kit Available for MAX19586
(Order MAX19586EVKIT)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
MAX19586ETN -40°C to +85°C 56 Thin QFN-EP T5688-2
MAX19586ETN+ -40°C to +85°C 56 Thin QFN-EP T5688-2
+Denotes lead-free package.
Pin Configuration
TOP VIEW
42 41 40 39 38 37 36 35 34 33 32 31 30 29
D9 43
28 AGND
D10 44
27 REFIN
D11 45
26 REFOUT
D12 46
D13 47
D14 48
D15 49
DAV 50
MAX19586
25 AVDD
24 AVDD
23 AVDD
22 AGND
21 AGND
DVDD 51
DGND 52
DOR 53
N.C. 54
AVDD 55
AVDD 56
20 AGND
19 AVDD
18 AVDD
17 AVDD
16 N.C.
15 N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
THIN QFN
8mm x 8mm
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
High-Dynamic-Range, 16-Bit,www.DataSheet4U.com
80Msps ADC with -82dBFS Noise Floor
Typical Operating Characteristics
(AVDD = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 5pF at
digital outputs, fCLK = 80MHz, TA = +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records and under coherent
sampling conditions.)
FFT PLOT
FFT PLOT
FFT PLOT
(32,768-POINT RECORD)
(32,768-POINT RECORD)
(261,244-POINT DATA RECORD)
00
0
fCLK = 80.00012288MHz
fCLK = 80.00012288MHz
fCLK = 80.00012288MHz
-20
fIN = 10.10011317MHz
AIN = -2.02dBFS
-20
fIN = 70.16368199MHz
AIN = -2.06dBFS
-20
fIN = 130.00050486MHz
AIN = -1.82dBFS
SNR = 80dB
SNR = 79.3dB
SNR = 77.7dB
-40
SINAD = 79.8dB
SFDR1 = 96.2dBc
-40
SINAD = 77.7dB
SFDR1 = 83.3dBc
-40 SINAD = 76.4dB
SFDR1 = 83.1dBc
SFDR2 = 101dBc
SFDR2 = 98.2dBc
-60 SFDR2 = 91.2dBc
-60
HD2 = -99.6dBc
-60
HD2 = -93.5dBc
HD2 = -89.4dBc
HD3 = -96.2dBc
HD3 = -83.3dBc
-80 HD3 = -83.1dBc
-80 -80
32
3 -100
-100
23
-100
2
-120
-120
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(fCLK = 80MHz, AIN = -2dBFS)
82
80
SNR
78
76 SINAD
74
72
70
0
20 40 60 80 100 120 140 160 180
fIN (MHz)
-120
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(fCLK = 80MHz, AIN = -2dBFS)
110
105
100 SFDR2
95
90
85
SFDR1
80
75
70
0
20 40 60 80 100 120 140 160 180
fIN (MHz)
-140
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fCLK = 80MHz, AIN = -2dBFS)
-70
-75
-80
HD3
-85
-90
-95 HD2
-100
-105
-110
0
20 40 60 80 100 120 140 160 180
fIN (MHz)
SNR vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 10.10011MHz)
85
80 SNR (dBFS)
75
70
65
60
55 SNR (dB)
50
45
40
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
SFDR1 vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 10.10011MHz)
120
SFDR1 (dBFS)
110
100
90
SFDR1 (dBc)
80
70
SFDR = 90dB
REFERENCE LINE
60
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
SFDR2 vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 10.10011MHz)
120
110 SFDR2 (dBFS)
100
90 SFDR2 (dBc)
80
70 SFDR = 90dB
REFERENCE LINE
60
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
_______________________________________________________________________________________ 5
5 Page 
High-Dynamic-Range, 16-Bit,www.DataSheet4U.com
80Msps ADC with -82dBFS Noise Floor
Clock Inputs (CLKP, CLKN)
The differential clock buffer for the MAX19586 has been
designed to accept an AC-coupled clock waveform.
Like the signal inputs, the clock inputs are self-biasing.
In this case, the self-biased potential is 1.6V and each
input is connected to the reference potential with a 5kΩ
resistor. Consequently, the differential input resistance
associated with the clock inputs is 10kΩ. While differ-
ential clock signals as low as 0.5VP-P can be used to
drive the clock inputs, best dynamic performance is
achieved with 1VP-P to 5VP-P clock input voltage levels.
Jitter on the clock signal translates directly to jitter
(noise) on the sampled signal. Therefore, the clock
source must be a very low-jitter (low-phase-noise)
source. Additionally, extremely low phase-noise oscilla-
tors and bandpass filters should be used to obtain the
true AC performance of this converter. See the
Differential, AC-Coupled Clock Inputs and Testing the
MAX19586 topics in the Applications Information sec-
tion for additional details on the subject of driving the
clock inputs.
T/H AMPLIFIER
INP
TO FIRST QUANTIZER
STAGE
5kΩ
OTA
5kΩ
INN
T/H AMPLIFIER
TO FIRST QUANTIZER
STAGE
Figure 2. Simplified Analog Input Architecture
System Timing Requirements
Figure 4 depicts the general timing relationships for the
signal input, clock input, data output, and DAV output.
Figure 5 shows the detailed timing specifications and
signal relationships, as defined in the Electrical
Characteristics table.
The MAX19586 samples the input signal on the rising
edge of the input clock. Output data is valid on the ris-
ing edge of the DAV signal, with a 7 clock-cycle data
latency. Note that the clock duty cycle should typically
be 50% ±10% for proper operation.
Digital Outputs (D0–D15, DAV, DOR)
Although designed for low-voltage 1.8V logic systems,
the logic-high level of the low-voltage CMOS-compati-
ble digital outputs (D0–D15, DAV, and DOR) offer some
flexibility, as it allows the user to select the digital volt-
age within the 1.7V to 1.9V range.
For best performance, the capacitive loading on the
digital outputs of the MAX19586 should be kept as low
as possible (< 10pF). Due to the current-limited data-
output driver of the MAX19586, large capacitive loads
increase the rise and fall time of the data and can make
it more difficult to register the data into the next IC. The
loading capacitance can be kept low by keeping the
output traces short and by driving a single CMOS
buffer or latch input (as opposed to multiple CMOS
inputs). The output data is in two’s-complement format,
as illustrated in Table 1.
Data is valid at the rising edge of DAV (Figures 4, 5).
DAV may be used as a clock signal to latch the output
data. Note that the DAV output driver is not current lim-
ited, hence it allows for higher capacitive loading.
2.56VP-P
DIFFERENTIAL FSR
INP
INN
-640mV
+640mV
COMMON-MODE
VOLTAGE (2.2V)
Figure 3. Full-Scale Voltage Range
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX19586.PDF ] | |
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