PDF MAX5878 Data sheet ( Hoja de datos )

Número de pieza	MAX5878
Descripción	16-Bit/ 250Msps -High-Dynamic-Performance/Dual DAC with LVDS Inputs
Fabricantes	Maxim Integrated Products
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No Preview Available ! 19-3591; Rev 0; 2/05 EVAALVUAAILTAIOBNLEKIT www.DataSheet4U.com 16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs General Description The MAX5878 is an advanced 16-bit, 250Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 76dBc spurious-free dynamic range (SFDR) at fOUT = 16MHz and supports update rates of 250Msps, with a power dissipation of only 296mW. The MAX5878 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and allows a 0.1VP-P to 1VP-P differential output voltage swing. The device features an integrated +1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an exter- nal reference source for optimum flexibility and improved gain accuracy. The clock inputs of the MAX5878 accept both LVDS and LVPECL-compatible voltage levels. The device fea- tures an interleaved data input that allows a single LVDS bus to support both DACs. The MAX5878 is avail- able in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended temperature range (-40°C to +85°C). Refer to the MAX5876* and MAX5877* data sheets for pin-compatible 12-bit and 14-bit versions of the MAX5878, respectively. Refer to the MAX5875 data sheet for a CMOS-compatible version of the MAX5878. Applications Base Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave Direct Digital Synthesis (DDS) Cable Modem Termination Systems (CMTS) Automated Test Equipment (ATE) Instrumentation Future product—contact factory for availability. Selector Guide PART MAX5873 MAX5874 MAX5875 MAX5876 MAX5877* MAX5878 RESOLUTION (BITS) 12 14 16 12 14 16 UPDATE RATE 200Msps 200Msps 200Msps 250Msps 250Msps 250Msps LOGIC INPUTS CMOS CMOS CMOS LVDS LVDS LVDS Features ♦ 250Msps Output Update Rate ♦ Noise Spectral Density = -164dBFS/Hz at fOUT = 16MHz ♦ Excellent SFDR and IMD SFDR = 76dBc at fOUT = 16MHz (to Nyquist) SFDR = 71dBc at fOUT = 80MHz (to Nyquist) IMD = -90dBc at fOUT = 10MHz IMD = -72dBc at fOUT = 80MHz ♦ ACLR = 75dB at fOUT = 61MHz ♦ 2mA to 20mA Full-Scale Output Current ♦ LVDS-Compatible Digital and Clock Inputs ♦ On-Chip +1.20V Bandgap Reference ♦ Low 296mW Power Dissipation ♦ Compact 68 QFN-EP Package (10mm x 10mm) ♦ Evaluation Kit Available (MAX5878EVKIT) Ordering Information PART TEMP RANGE PIN- PACKAGE PKG CODE MAX5878EGK -40°C to +85°C 68 QFN-EP G6800-4 EP = Exposed pad. Pin Configuration TOP VIEW 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 B4N B3P B3N B2P B2N B1P B1N B0P B0N GND DVDD3.3 GND GND AVDD3.3 GND REFIO FSADJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MAX5878 51 B12P 50 B13N 49 B13P 48 B14N 47 B14P 46 B15N 45 B15P 44 SELIQN 43 SELIQP 42 XORP 41 XORN 40 PD 39 TORB 38 CLKP 37 CLKN 36 GND 35 AVCLK 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 QFN ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 page www.DataSheet4U.com 16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) (AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out- put load 50Ω double-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Differential Input Slew Rate External Common-Mode Voltage Range Input Resistance Input Capacitance POWER SUPPLIES Analog Supply Voltage Range Digital Supply Voltage Range Analog Supply Current Digital Supply Current Power Dissipation Power-Supply Rejection Ratio SYMBOL SRCLK (Note 8) VCOM RCLK CCLK CONDITIONS AVDD3.3 AVDD1.8 DVDD3.3 DVDD1.8 IAVDD3.3 fDAC = 250Msps, fOUT = 16MHz Power-down IAVDD1.8 fDAC = 250Msps, fOUT = 16MHz Power-down IDVDD3.3 fDAC = 250Msps, fOUT = 16MHz Power-down IDVDD1.8 fDAC = 250Msps, fOUT = 16MHz Power-down PDISS fDAC = 250Msps, fOUT = 16MHz Power-down PSRR AVDD3.3 = AVCLK = DVDD3.3 = +3.3V ±5% (Notes 8, 9) MIN TYP MAX >100 AVCLK / 2 ±0.3 5 2.5 UNITS V/µs V kΩ pF 3.135 3.3 3.465 1.710 1.8 1.890 V 3.135 3.3 3.465 1.710 1.8 1.890 V 52 56 mA 1 µA 32 36 mA 1 µA 0.2 1 mA 1 µA 36 40 mA 4 µA 296 324 mW 16 µW -0.1 +0.1 %FS/V Note 2: Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design. Note 3: Nominal full-scale current IOUTFS = 32 x IREF. Note 4: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5878. Note 5: Parameter measured single-ended into a 50Ω termination resistor. Note 6: Not production tested. Guaranteed by design. Note 7: No termination resistance between XORP and XORN. Note 8: A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance. Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage. _______________________________________________________________________________________ 5 5 Page www.DataSheet4U.com 16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs Detailed Description Architecture The MAX5878 high-performance, 16-bit, dual current- steering DAC (Figure 1) operates with DAC update rates up to 250Msps. The converter consists of input registers and a demultiplexer for single-port operation, followed by a current-steering array. During operation, the input data registers demultiplex the single-port data bus. The cur- rent-steering array generates differential full-scale cur- rents in the 2mA to 20mA range. An internal current-switching network, in combination with external 50Ω termination resistors, converts the differential output currents into dual differential output voltages with a 0.1V to 1V peak-to-peak output voltage range. An integrated +1.2V bandgap reference, control amplifier, and user- selectable external resistor determine the data convert- er’s full-scale output range. Reference Architecture and Operation The MAX5878 supports operation with the internal +1.2V bandgap reference or an external reference volt- age source. REFIO serves as the input for an external, low-impedance reference source. REFIO also serves as a reference output when the DAC operates in internal reference mode. For stable operation with the internal reference, decouple REFIO to GND with a 1µF capaci- tor. Due to its limited output drive capability, buffer REFIO with an external amplifier when driving large external loads. DVDD3.3 DATA15– DATA0 TORB SELIQP SELIQN XORP XORN LVDS RECEIVER AVCLK CLKP CLKN DVDD1.8 AVDD1.8 LATCH LATCH XOR/ DECODE LATCH XOR/ DECODE CLK INTERFACE POWER-DOWN BLOCK PD MAX5878 AVDD3.3 LATCH LATCH DAC OUTIP OUTIN LATCH LATCH DAC OUTQP OUTQN +1.2V REFERENCE DACREF REFIO FSADJ GND Figure 1. MAX5878 High-Performance, 16-Bit, Dual Current-Steering DAC ______________________________________________________________________________________ 11 11 Page

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