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PDF LTC1747 Data sheet ( Hoja de datos )
| Número de pieza | LTC1747 | |
| Descripción | 12-Bit 80Msps Low Noise ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Sample Rate: 80Msps
s 72dB SNR and 85dB SFDR (3.2V Range)
s 70.5dB SNR and 87dB SFDR (2V Range)
s Pin Compatible with 14-Bit 80Msps LTC1748
s No Missing Codes
s Single 5V Supply
s Power Dissipation: 1.4W
s Selectable Input Ranges: ±1V or ±1.6V
s 240MHz Full Power Bandwidth S/H
s Pin Compatible Family
25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
s 48-Pin TSSOP Package
U
APPLICATIO S
s Telecommunications
s Receivers
s Cellular Base Stations
s Spectrum Analysis
s Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC1747www.DataSheet4U.com
12-Bit, 80Msps Low Noise ADC
DESCRIPTIO
The LTC®1747 is an 80Msps, sampling 12-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. Pin selectable input ranges of ±1V
and ±1.6V along with a resistor programmable mode
allow the LTC1747’s input range to be optimized for a wide
variety of applications.
The LTC1747 is perfect for demanding communications
applications with AC performance that includes 72dB
SNR and 85dB spurious free dynamic range. Ultralow jitter
of 0.15psRMS allows undersampling of IF frequencies with
excellent noise performance. DC specs include ±1.5 LSB
INL and ±0.8LSB DNL over temperature.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to any low voltage
DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
BLOCK DIAGRA
AIN+
±1V
DIFFERENTIAL
ANALOG INPUT AIN–
SENSE
RANGE
SELECT
VCM
4.7µF
2.35VREF
80Msps, 12-Bit ADC with a 2V Differential Input Range
S/H
12-BIT
CORRECTION
LOGIC AND
12
OUTPUT
AMP
PIPELINED ADC
SHIFT
LATCHES
REGISTER
OVDD
0.1µF
OF
•••
D11
D0
CLKOUT
OGND
0.5V
TO 5V
0.1µF
BUFFER
DIFF AMP
CONTROL LOGIC
VDD
1µF
5V
1µF
1µF
GND
REFLB
0.1µF
1µF
REFHA
4.7µF
REFLA REFHB ENC ENC MSBINV
0.1µF DIFFERENTIAL
1µF ENCODE INPUT
1747 BD
OE
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LTC1747www.DataSheet4U.com
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 80MHz, differential ENC/ENC = 2VP-P 80MHz
sine wave, input range = ±1.6V differential, unless otherwise specified.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
TYPICAL PERFOR A CE CHARACTERISTICS
INL, 3.2V Range
1
TA = 25°C
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
1747 G01
DNL, 3.2V Range
1
TA = 25°C
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
1747 G02
Averaged 8192 Point FFT,
5.2MHz Input, –1dB, 3.2V Range
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
TA = 25°C
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
1747 G04
Averaged 8192 Point FFT,
5.2MHz Input, –10dB, 3.2V Range
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
TA = 25°C
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
1747 G05
Averaged 8192 Point FFT,
5.2MHz Input, –20dB, 3.2V Range
0
–10
TA = 25°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
1747 G06
1747fa
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LTC1747www.DataSheet4U.com
APPLICATIO S I FOR ATIO
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π) • FIN • TJITTER
CONVERTER OPERATION
The LTC1747 is a CMOS pipelined multistep converter.
The converter has four pipelined ADC stages; a sampled
analog input will result in a digitized value five cycles later,
see the Timing Diagram section. The analog input is
differential for improved common mode noise immunity
and to maximize the input range. Additionally, the differen-
tial input drive will reduce even order harmonics of the
sample-and-hold circuit. The encode input is also
differential for improved common mode noise immunity.
The LTC1747 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
AIN+
INPUT
AIN– S/H
VCM
4.7µF
2.35V
REFERENCE
RANGE
SELECT
SENSE
REF
BUF
FIRST PIPELINED
ADC STAGE
(5 BITS)
DIFF
REF
AMP
SECOND PIPELINED
ADC STAGE
(4 BITS)
THIRD PIPELINED
ADC STAGE
(4 BITS)
REFL
REFH INTERNAL CLOCK SIGNALS
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
CONTROL LOGIC
AND
CALIBRATION LOGIC
REFLB REFHA
0.1µF
4.7µF
1µF
REFLA REFHB ENC
0.1µF
1µF
ENC
MSBINV
OE
Figure 1. Functional Block Diagram
FOURTH PIPELINED
ADC STAGE
(2 BITS)
SHIFT REGISTER
AND CORRECTION
OUTPUT
DRIVERS
OVDD 0.5V TO
5V
OF
D11
D0
CLKOUT
OGND
1747 F01
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11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC1747.PDF ] | |
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