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PDF STCD1040 Data sheet ( Hoja de datos )
| Número de pieza | STCD1040 | |
| Descripción | Multi-channel clock distribution circuit | |
| Fabricantes | STMicroelectronics | |
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STCD1020, STCD1030, STCD1040
Multi-channel clock distribution circuit
Features
■ 2, 3 or 4 outputs buffered clock distribution
■ Single-ended sine wave or square wave clock
input and output
■ Individual clock enable for each output
■ Lower fan-out on clock source
■ No AC coupling capacitor needed at the input
■ Ultra-low phase noise and standby current
■ 2.5 V to 3.6 V supply voltage(a)
■ 10 pF typical load driving capability
■ Available in TDFN packages
– STCD1020 - 8-lead (2 mm x 2 mm)
– STCD1030 - 10-lead (2 mm x 2.5 mm)
– STCD1040 - 12-lead (2 mm x 3 mm)
■ Operational temperature : –40°C to 85°C
Applications
■ Multi-mode RF clock reference
■ Baseband peripheral devices clock reference
TDFN (8, 10 or 12 lead)
Description
The STCD1020, STCD1030 and STCD1040 are
2, 3 or 4 outputs unity gain clock distribution
circuits, which are used to provide a common
frequency clock to multi-mode mobile RF
applications. It can also be used for those
baseband peripheral applications in a mobile
phone such as WLAN, Bluetooth, GPS and DVB-
H as a clock reference. The STCD1020,
STCD1030 and STCD1040 isolate each device
driven by their clock outputs and minimize
interference between the devices. Each of the
clock buffers can be disabled to lower the power
consumption if the connected device does not
need the clock. The STCD1020, STCD1030 and
STCD1040 accept commonly used mobile master
clock frequencies ranging from 10 MHz to 52
MHz.
a. For the 1.65 to 2.75 V version, please contact local ST
sales office
The STCD1020, STCD1030 and STCD1040 are
available in 2 mm x 2 mm 8-lead, 2 mm x 2.5 mm
10-lead and 2 mm x 3 mm 12-lead TDFN
packages and can be operated with a single 2.8 V
(or 1.8 V) supply. The operational temperature is
–40°C to +85°C.
Table 1. Device summary
Order code
Operating temperature range Channel
Supply
Package
STCD1020RDG6E
–40°C to 85°C
2 2.8 V
TDFN8
STCD1030RDH6E
STCD1040RDM6F
–40°C to 85°C
–40°C to 85°C
3 2.8 V
4 2.8 V
TDFN10
TDFN12
May 2008
Rev 4
1/40
www.st.com
1
1 page  
STCD1020, STCD1030, STCD1040
List of figures
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
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STCD10x0 recovery time from standby to active (STCD1040, 1.8 V version,
EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1) . . . . . . . . . . . . . . . . . . . . . . . . 27
STCD10x0 buffer recovery time from off to on (STCD1040, 1.8 V version,
EN2 =EN3=EN4=1, measure CLK1 when EN1 from 0 to 1). . . . . . . . . . . . . . . . . . . . . . . . 28
Sine wave input clock vs. output clock (STCD1040, 1.8 V version, 26 MHz sine wave
master clock input from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Rise and fall time for square wave output (STCD1040, 1.8 V version, 10MHz square wave
master clock input, Cload = 20 pF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Input clock phase noise (STCD1040, 1.8 V version, 26 MHz master clock input
from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output clock phase noise (STCD1040, 1.8 V version, this phase noise includes the
additive phase noise from TCXO and STCD1040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock bandwidth (STCD1040, 1.8 V version, Cload = 10 pF) . . . . . . . . . . . . . . . . . . . . . . . 30
TDFN - 8-lead, 2 x 2 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TDFN - 10-lead, 2 x 2.5 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TDFN - 12-lead, 2 x 3 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5/40
5 Page 
STCD1020, STCD1030, STCD1040
3 Application information
Application information
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3.1
Typical applications
The STCD1020, STCD1030 and STCD1040 distribute a source clock (for example, from
VCTCXO) to 2, 3 or 4 channel outputs. The typical application circuits using STCD1040 are
shown in Figure 7 and Figure 8 below.
In Figure 7, the clock from VCTCXO is distributed to the TD-SCDMA transmitter and
receiver and GSM transceiver separately.
In Figure 8, the buffer #4 output is fed into the Bluetooth system. In order to allow minimum
power consumption, a Bluetooth system always has a clock request feature. If the Bluetooth
system does not require the clock, the clock request will disable the clock output.
The enable pins can also be connected to logic high to let the channel output always on. If
the channels of STCD1020, STCD1030 and STCD1040 are not used in the application, the
enable pins of the channels should be connected to ground on PCB.
Figure 7.
Typical application circuit using STCD1040 for RF ends of TD-
SCDMA/GSM dual mode mobile phone
VCC
VCTCXO
VCC
STCD1040 EN4
CLK4
EN3
MCLK
CLK3
EN2
CLK2
EN1
GND CLK1
Mode
selection
TD-SCDMA
transmitter
TD-SCDMA
receiver
GSM
transceiver
ai13954
11/40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STCD1040.PDF ] | |
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