PDF ISPLSI5128VE Data sheet ( Hoja de datos )

Número de pieza	ISPLSI5128VE
Descripción	In-System Programmable 3.3V SuperWIDE High Density PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! www.DataSheet4U.com ispLSI® 5128VE In-System Programmable 3.3V SuperWIDE™ High Density PLD Features • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 6000 PLD Gates / 128 Macrocells — 96 I/O Pins Available — 128 Registers — High-Speed Global Interconnect — SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels — Electrically Erasable and Reprogrammable — Non-Volatile — Programmable Speed/Power Logic Path Optimization • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE • ARCHITECTURE FEATURES — Enhanced Pin-Locking Architecture with Single- Level Global Routing Pool and SuperWIDE GLBs — Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell — Macrocells Support Concurrent Combinatorial and Registered Functions — Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable — Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks — Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options — Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell Functional Block Diagram Input Bus Generic Logic Block Boundary Scan Interface Global Routing Pool (GRP) Generic Logic Block Input Bus ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are pro- vided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be by- passed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com January 2002 5128ve_05 1 1 page www.DataSheet4U.com Specifications ispLSI 5128VE Figure 3. ispLSI 5000VE Generic Logic Block (GLB) From GRP 0 1 2 66 67 PT 0 PT 1 PT 2 PT 3 PT 4 PT 9 PT 8 PT 7 PT 6 PT 5 PTSA Global PTOE Bus Macrocell 0 From PTSA PTSA bypass To I/O Pad PTOE PT Clock PT Reset PT Preset Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 4 Macrocell 1 From PTSA PTSA bypass To GRP To I/O Pad PTOE PT Clock PT Reset PT Preset Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 4 To GRP PT 79 PT 78 PT 77 PT 76 PT 75 Macrocell 15 From PTSA PTSA bypass PTOE PT Clock PT Reset PT Preset Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 4 To I/O Pad To GRP PT 159 PT 158 PT 157 PT 156 PT 155 PT 160 PT 161 PT 162 Macrocell 31 From PTSA PTSA bypass PTOE PT Clock PT Reset PT Preset Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 4 To I/O Pad To GRP 5 5 Page www.DataSheet4U.com Specifications ispLSI 5128VE Switching Test Conditions Input Pulse Levels Input Rise and Fall Time GND to VCCIOmin ≤ 1.5ns 10% to 90% Input Timing Reference Levels 1.5V Ouput Timing Reference Levels 1.5V Output Load 3-state levels are measured 0.5V from steady-state active level. See Figure 9 Table 2-0003/5KVE Figure 9. Test Load Device Output VCCIO R1 R2 Output Load Conditions (See Figure 9) Test Point CL* TEST CONDITION A Active High B Active Low Active High to Z C at VOH-0.5V Active Low to Z at VOL+0.5V D Slow Slew 3.3V 2.5V R1 R2 R1 R2 CL 316Ω 348Ω 511Ω 475Ω 35pF ∞ 348Ω ∞ 475Ω 35pF 316Ω ∞ 511Ω ∞ 35pF ∞ 348Ω ∞ 475Ω 5pF *CL includes Test Fixture and Probe Capacitance. 0213D 316Ω ∞ 511Ω ∞ 5pF ∞ ∞ ∞ ∞ 35pF Table 2-0004A/5KVE DC Electrical Characteristics for 3.3V Range1 Over Recommended Operating Conditions SYMBOL PARAMETER VCCIO I/O Reference Voltage VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage 1. I/O voltage configuration must be set to VCC. CONDITION VCCIO = min, IOL = 8 mA VCCIO = min, IOH = -4 mA MIN. 3.0 -0.3 2.0 – 2.4 TYP. – – – – – MAX. UNITS 3.6 V 0.8 V 5.25 V 0.4 V –V Table 2-0007/5KVE 11 11 Page

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