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PDF LTC6800 Data sheet ( Hoja de datos )
| Número de pieza | LTC6800 | |
| Descripción | Instrumentation Amplifier | |
| Fabricantes | Linear Technology | |
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FEATURES
s 116dB CMRR Independent of Gain
s Maximum Offset Voltage: 100µV
s Maximum Offset Voltage Drift: 250nV/°C
s – 40°C to 125°C Operation
s Rail-to-Rail Input Range
s Rail-to-Rail Output Swing
s Supply Operation: 2.7V to 5.5V
s Available in an MS8 and 3mm × 3mm × 0.8mm
DFN Packages
U
APPLICATIO S
s Thermocouple Amplifiers
s Electronic Scales
s Medical Instrumentation
s Strain Gauge Amplifiers
s High Resolution Data Acquisition
LTC6800
Rail-to-Rail
Input and Output,
Instrumentation Amplifier
DESCRIPTIO
The LTC®6800 is a precision instrumentation amplifier.
The CMRR is typically 116dB with a single 5V supply and
is independent of gain. The input offset voltage is guaran-
teed below 100µV with a temperature drift of less than
250nV/°C. The LTC6800 is easy to use; the gain is adjust-
able with two external resistors, like a traditional op amp.
The LTC6800 uses charge balanced sampled data tech-
niques to convert a differential input voltage into a single
ended signal that is in turn amplified by a zero-drift
operational amplifier.
The differential inputs operate from rail-to-rail and the
single ended output swings from rail-to-rail. The LTC6800
is available in an MS8 surface mount package. For space
limited applications, the LTC6800 is available in a
3mm × 3mm × 0.8mm dual fine pitch leadless package
(DFN).
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
High Side Power Supply Current Sense
VREGULATOR
1.5mΩ
2– 8
LTC6800
7
3 + 6 10k
5
4
0.1µF
150Ω
OUT
100mV/A
OF LOAD
CURRENT
ILOAD LOAD
6800 TA01
Typical Input Referred Offset vs
Input Common Mode Voltage (VS = 3V)
15
VS = 3V
VREF = 0V
10 TA = 25°C
5
0
–5
–10
–15
0
G = 1000
G = 100
G = 10
G=1
0.5 1 1.5 2 2.5 3
INPUT COMMON MODE VOLTAGE (V)
6800 TA02
6800fa
1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS
LTC6800
Additional Input Offset Due to Input
www.datashMReSoetdM4euis.(cmCoImaNtc<h1v0s0pInFp)ut Common
40
VS = 5V
RIN+ = 0k, RIN– = 20k
30 VREF = 0V
CIN < 100pF
RIN+ = 0k, RIN– = 15k
20
10
G = 10
TA = 25°C
RIN+ = 0k, RIN– = 10k
RIN+ = 10k, RIN– = 0k
0
–10 RIN+ = 15k, RIN– = 0k
R+ RIN+ = 20k, RIN– = 0k
–20 +
SMALL CIN
–30 –
R–
–40
01 2 3 4
INPUT COMMON MODE VOLTAGE (V)
5
6800 G10
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN > 1µF)
200 VS = 3V
150
VREF = 0V
TA = 25°C
100 G = 10
R+ = 0Ω, R– = 1k
R+ = 0Ω, R– = 500Ω
50 R+ = 0Ω, R– = 100Ω
0
R+ = 100Ω, R– = 0Ω
–50
R+ = 500Ω, R– = 0Ω
–100
R+
–150 BIG CIN
R–
+
–
R+ = 1k, R– = 0Ω
–200
0 0.5 1.0 1.5 2.0 2.5 3.0
INPUT COMMON MODE VOLTAGE (V)
6800 G13
VOS vs VREF
30
VIN+ = VIN– = REF
G = 10
20 TA = 25°C
10
0
VS = 3V
–10
VS = 5V
–20
–30
0
123
VREF (V)
4
6800 G16
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN > 1µF)
40
VS = 3V
30
RVR+E=F
= 0V
R– =
RS
20
CIN > 1µF
G = 10
RS = 15k
RS = 10k
10 TA = 25°C
RS = 5k
0
–10
–20 RS
BIG CIN
–30
+
–
–40 RS
0 0.5 1.0 1.5 2.0 2.5
INPUT COMMON MODE VOLTAGE (V)
3.0
6800 G11
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN > 1µF)
200 VS = 5V
150
VREF = 0V
TA = 25°C
100 G = 10
50
R+ = 0Ω, R– = 1k
R+ = 0Ω, R– = 500Ω
R+ = 0Ω, R– = 100Ω
0
–50
–100
R+
BIG CIN
–150
–200
0
R–
1
R+ = 100Ω, R– = 0Ω
R+ = 500Ω, R– = 0Ω
+ R+ = 1k, R– = 0Ω
–
23 4
INPUT COMMON MODE VOLTAGE (V)
5
6800 G14
Gain Nonlinearity, G = 1
10
VS = ±2.5V
8 VREF = 0V
6
G=1
RL = 10k
4 TA = 25°C
2
0
–2
–4
–6
–8
–10
–2.4 –1.9 –1.4 –0.9 –0.4 0.1 0.6 1.1 1.6
OUTPUT VOLTAGE (V)
6800 G17
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN > 1µF)
70
RS = 10k
50
30 RS = 5k
10 RS = 1k
–10 RS = 500Ω
–30 RS
–50 BIG CIN
–70
0
RS
1
+
–
2
VS = 5V
VRR+E=F
= 0V
R– =
RS
CIN > 1µF
G = 10
TA = 25°C
34 5
INPUT COMMON MODE VOLTAGE (V)
6800 G12
Offset Voltage vs Temperature
80
60
40
20
0
VS = 3V
–20
VS = 5V
–40
–60
–80
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
6800 G15
Gain Nonlinearity, G = 10
10
VS = ±2.5V
8 VREF = 0V
6
G = 10
RL = 10k
4 TA = 25°C
2
0
–2
–4
–6
–8
–10
–2.4
–1.4 –0.4 0.6 1.6
OUTPUT VOLTAGE (V)
2.6
6800 G18
6800fa
5
5 Page 
LTC6800
PACKAGE DESCRIPTIO
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MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.254
(.010)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1.10
(.043)
MAX
0.86
(.034)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP 0.65
(.0256)
BSC
4.90 ± 0.152
0.127 ± 0.076 (.193 ± .006)
(.005 ± .003)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
8 7 65
0.52
(.0205)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
5.23
(.206)
MIN
0.889 ± 0.127
(.035 ± .005)
3.20 – 3.45
(.126 – .136)
1 234
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
RECOMMENDED SOLDER PAD LAYOUT
MSOP (MS8) 0603
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
5
0.38 ± 0.10
8
0.675 ±0.05
PIN 1
TOP MARK
3.00 ±0.10 1.65 ± 0.10
(4 SIDES) (2 SIDES)
0.200 REF
0.75 ±0.05
0.00 – 0.05
4
0.28 ± 0.05
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.28 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
(DD8) DFN 0203
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
6800fa
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC6800.PDF ] | |
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