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PDF MT47H128M16 Data sheet ( Hoja de datos )
| Número de pieza | MT47H128M16 | |
| Descripción | (MT47HxxxMxx) DDR2 SDRAM | |
| Fabricantes | Micron | |
| Logotipo |  |
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2Gb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H512M4 – 64 Meg x 4 x 8 banks
MT47H256M8 – 32 Meg x 8 x 8 banks
MT47H128M16 – 16 Meg x 16 x 8 banks
Features
• Vdd = +1.8V ±0.1V, VddQ = +1.8V ±0.1V
www.DataShe•etJ4EUD.cEomC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Duplicate output strobe (RDQS) option for x8
• DLL to align DQ and DQS transitions with CK
• 8 internal banks for concurrent operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Industrial temperature (IT) option
• RoHS compliant
• Supports JEDEC clock jitter specification
Options1
Marking
• Configuration
– 512 Meg x 4 (64 Meg x 4 x 8 banks)
– 256 Meg x 8 (32 Meg x 8 x 8 banks)
– 128 Meg x 16 (16 Meg x 16 x 8 banks)
• FBGA package (Pb-free) – x16
– 84-ball FBGA (11.5mm x 14mm) Rev. A
• FBGA package (Pb-free) – x4, x8
– 60-ball FBGA (11.5mm x 14mm) Rev. A
• Timing – cycle time
– 3.0ns @ CL = 4 (DDR2-667)
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)
– 5.0ns @ CL = 3 (DDR2-400)
• Self refresh
– Standard
– Low-power
• Operating temperature
– Commercial (0°C ≤ TC ≤ 85°C)
– Industrial (–40°C ≤ TC ≤ 95°C;
–40°C ≤ TA ≤ 85°C)
• Revision
512M4
256M8
128M16
HG
HG
-3E
-3
-37E
-5E
None
L
None
IT
:A
Note:
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on www.micron.com for
product offerings and availability.
Table 1: Key Timing Parameters
Speed Grade
-3E
-3
-37E
-5E
CL = 3
400
400
400
400
Data Rate (MHz)
CL = 4
667
533
533
400
CL = 5
667
667
n/a
n/a
tRCD (ns)
12
15
15
15
tRP (ns)
12
15
15
15
tRC (ns)
54
55
55
55
PDF: 09005aef824f87b6
Rev. B 9/08 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
2Gb: x4, x8, x16 DDR2 SDRAM
List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 16
Table 4: Input Capacitance ............................................................................................................................ 22
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 23
Table 6: Temperature Limits .......................................................................................................................... 24
Table 7: Thermal Impedance ......................................................................................................................... 25
Table 8: General Idd Parameters .................................................................................................................... 26
Table 9: Idd7 Timing Patterns (8-Bank Interleave READ Operation) ................................................................ 27
Table 10: DDR2 Idd Specifications and Conditions ......................................................................................... 28
www.DataSheTeat4bUle.co1m1: AC Operating Specifications and Conditions .................................................................................... 30
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 41
Table 13: ODT DC Electrical Characteristics ................................................................................................... 42
Table 14: Input DC Logic Levels ..................................................................................................................... 43
Table 15: Input AC Logic Levels ..................................................................................................................... 43
Table 16: Differential Input Logic Levels ........................................................................................................ 44
Table 17: Differential AC Output Parameters .................................................................................................. 46
Table 18: Output DC Current Drive ................................................................................................................ 46
Table 19: Output Characteristics .................................................................................................................... 47
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................ 48
Table 21: Full Strength Pull-Up Current (mA) ................................................................................................. 49
Table 22: Reduced Strength Pull-Down Current (mA) ..................................................................................... 50
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 51
Table 24: Input Clamp Characteristics ........................................................................................................... 52
Table 25: Address and Control Balls ............................................................................................................... 53
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 53
Table 27: AC Input Test Conditions ................................................................................................................ 54
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH) ................................................... 56
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH) .......................................... 57
Table 30: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ..................................................... 60
Table 31: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................ 62
Table 32: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb .................................................. 63
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-667 ...................................... 63
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-533 ...................................... 64
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-400 ...................................... 64
Table 36: Truth Table – DDR2 Commands ..................................................................................................... 69
Table 37: Truth Table – Current State Bank n – Command to Bank n ............................................................... 70
Table 38: Truth Table – Current State Bank n – Command to Bank m .............................................................. 72
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 73
Table 40: Burst Definition .............................................................................................................................. 78
Table 41: READ Using Concurrent Auto Precharge ......................................................................................... 99
Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 105
Table 43: Truth Table – CKE ......................................................................................................................... 120
PDF: 09005aef824f87b6
Rev. B 9/08 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
5 Page 
2Gb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams
Functional Block Diagrams
The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-
nally configured as a multibank DRAM.
Figure 3: Functional Block Diagram – 512 Meg x 4
ODT
www.DataSheet4U.comCKE
CK
CK#
CS#
RAS#
CAS#
WE#
Control
logic
Mode
registers
18
A0–A14,
BA0–BA2
18
Address
register
Refresh
counter
15
15
3
11
15
Row-
address
MUX
Bank 7
Bank 7
Bank 6
Bank 6
Bank 5
Bank 5
Bank 4
Bank 4
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank 0
Bank 0
row-
address
latch
32,768
Memory array
(32,768 x 512 x 16)
and
decoder
Sense amplifiers
8,192
16
2
Bank
control
logic
I/O gating
DM mask logic
512
(x16)
COL0, COL1
CK, CK#
4
16 Read
latch
4
4
4
4
MUX DATA
DLL
DRVRS
DQS 2
generator DQS, DQS#
Input
registers
11
Write
FIFO
16
and
drivers
1
41
Mask 1
4
1
11
1 RCVRS
4
Column-
address
counter/
latch
9
2
Column
decoder
CK, CK#
CK out
CK in
16
Data
4
4
4
COL0, COL1
44
4
4
2
ODT control Vdd Q
sw1 sw2 sw3
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
DQ0–DQ3
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
DQS, DQS#
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
DM
Vss Q
PDF: 09005aef824f87b6
Rev. B 9/08 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
11 Page | ||
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