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PDF MTP75N03HDL Data sheet ( Hoja de datos )
| Número de pieza | MTP75N03HDL | |
| Descripción | TMOS POWER FET | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTP75N03HDL/D
Advanced Information
HDTMOS E-FET ™
High Density Power FET
N–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS E–FET is designed to
withstand high energy in the avalanche and commutation modes.
This new energy efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for low–voltage,
high–speed switching applications in power supplies, converters
and PWM motor controls, and inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
www.DataSheet4wUh.ceorme inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.
• Ultra Low RDS(on), High–Cell Density, HDTMOS
• SPICE Parameters Available
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Avalanche Energy Specified
™
D
MTP75N03HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
75 AMPERES
RDS(on) = 9.0 mOHM
25 VOLTS
G
CASE 221A–06, Style 5
TO–220AB
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Single Pulse (tp ≤ 10 ms)
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
Value
25
25
± 15
± 20
75
59
225
150
1.0
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)
TJ, Tstg
EAS
– 55 to 175
280
Thermal Resistance — Junction to Case
— Junction to Ambient
RθJC
RθJA
1.0
62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
°C
mJ
°C/W
°C
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1
1 page  
7 28
6
5
Q1
4
24
QT
20
Q2 VGS
16
3 12
2
TJ = 25°C
ID = 75 A
8
14
Q3
0
VDS 0
0 10 20 30 40 50 60 70
QT, TOTAL GATE CHARGE (nC)
Figure 8. Gate–To–Source and Drain–To–Source
www.DataSheet4U.com
Voltage versus Total Charge
10000
1000
100
MTP75N03HDL
TJ = 25°C
ID = 75 A
VDD = 15 V
tr VGS = 5 V
tf
td(off)
td(on)
10
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de-
vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
di/dts. The diode’s negative di/dt during ta is directly con-
trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac-
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re-
covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen-
erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
75
TJ = 25°C
60 VGS = 0 V
45
30
15
0
0.5 0.6 0.7
0.8 0.9
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
Motorola TMOS Power MOSFET Transistor Device Data
5
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