|
|
PDF MT8VDDT3264HD Data sheet ( Hoja de datos )
| Número de pieza | MT8VDDT3264HD | |
| Descripción | (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms | |
| Fabricantes | Micron Semiconductor Products | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT8VDDT3264HD (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
SMALL-OUTLINE
DDR SDRAM MODULE
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Fast data transfer rates PC1600, PC2100, or PC2700
www.DataShe•et4UUt.ciloimzes 200 MT/s, 266 MT/s, and 333MT/s DDR
SDRAM components
• 128MB (16 Meg x 64), 256MB (32 Meg x 64), or
512MB (64 Meg x 64)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes
• 15.6µs (128MB), 7.8125µs (256MB and 512MB)
maximum average periodic refresh interval
• Gold edge contacts
128MB, 256MB, 512MB (x64)
200-PIN DDR SODIMM
MT8VDDT1664HD – 128MB
MT8VDDT3264HD – 256MB
MT8VDDT6464HD – 512MB
For the latest data sheet, please refer to the Micronâ Web
site: www.micron.com/moduleds
Figure 1: 200-Pin SODIMM (MO-224)
OPTIONS
MARKING
• Package
200-pin SODIMM (Standard)
200-pin SODIMM (Lead-free)1
• Frequency/CAS Latency2
6ns/166 MHz (333MT/s) CL=2.5
7.5ns/133 MHz (266 MT/s) CL = 2
7.5ns/133 MHz (266 MT/s) CL = 2
7.5ns/133 MHz (266 MT/s) CL = 2.5
10ns/100 MHz (200 MT/s) CL = 2
G
Y
-335
-262
-26A
-265
-202
NOTE: 1. Consult with factory for availability of lead-free
products.
2. CL = CAS (READ) Latency
Table 1: Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
128MB
4K
4K (A0–A11)
4 (BA0, BA1)
8 Meg x 16
512 (A0–A8)
2 (S0#, S1#)
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
16 Meg x 16
512 (A0–A8)
2 (S0#, S1#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 16
1K (A0–A9)
2 (S0#, S1#)
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
1 ©2003 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1 page  
128MB, 256MB, 512MB (x64)
200-PIN DDR SODIMM
Table 5: Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information
PIN NUMBERS
5, 6, 7, 8, 13, 14, 17, 18,
19, 20, 23, 20, 29, 30, 31,
32, 41, 42, 43, 44, 49, 50,
53, 54, 55, 56, 59, 60, 65,
66, 67, 67, 127, 128, 129,
130, 135, 136, 139, 140,
141, 142, 145, 146, 151,
www.DataShee11t456U25.,,co11m5636,,
154,
171,
163,
172,
164,
175,
176, 177, 178, 181, 182,
187, 188, 189, 190
195
194, 196, 198
193
1, 2
9, 10, 21, 22, 33, 34, 36,
45, 46, 57, 58, 69, 70, 81,
82, 92, 93, 94, 113, 114,
131, 132, 143, 144, 155,
156, 157, 167, 168, 179,
180, 191, 192
3, 4, 15, 16, 27, 28, 38, 39,
40, 51, 52, 63, 64, 75, 76,
87, 88, 90, 103, 104, 125,
126, 137, 138, 149, 150,
159, 161, 162, 173, 174,
185, 186
197
71, 72, 73, 74, 77, 78, 79,
80, 83, 84
85, 97, 98,
99 (128MB only), 123,
124, 199, 200
SYMBOL
DQ0-DQ63
TYPE
Input/ Data I/Os: Data bus.
Output
DESCRIPTION
SCL
SA0-SA2
SDA
VREF
VDD
Input Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-
detect portion of the module.
Input SSTL_2 reference voltage.
Supply Power Supply: +2.5V ±0.2V.
See note 50 on page 23.
VSS Supply Ground.
VDDSPD
DNU
NC
Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
— Do Not Use: These pins are not connected on these modules,
but are assigned pins on other modules in this product family.
— No Connect: These pins should be left unconnected.
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
5 Page 
Commands
The Truth Tables below provides a general reference
of available commands. For a more detailed descrip-
128MB, 256MB, 512MB (x64)
200-PIN DDR SODIMM
tion of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data sheet.
Table 8: Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH
NAME (FUNCTION)
DESELECT (NOP)
w w w . D aNOt aOSPEhRAeTIeONt 4(NUOP.) c o m
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
CS# RAS# CAS# WE#
ADDR
HXXX
X
L HHH
X
L L H H Bank/Row
L H L H Bank/Col
L H L L Bank/Col
L HH L
X
L LHL
Code
L L LH
X
L L L L Op-Code
NOTES
1
1
2
3
3
4
5
6, 7
8
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB ) provide row address.
3. BA0–BA1 provide device bank address; A0–A8 (128MB, 256MB) or A0–A9 (512MB), provide column address; A10 HIGH
enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–
A12 (256MB, 512MB) provide the op-code to be written to the selected mode register.
Table 9: DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
DM DQS
L Valid
HX
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT8VDDT3264HD.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT8VDDT3264H | (MT8VDDT1664H / MT8VDDT3264H) 200-Pin DDR Sdram Sodimms | Micron Semiconductor Products |
| MT8VDDT3264HD | (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms | Micron Semiconductor Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |