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PDF MT47H256M4 Data sheet ( Hoja de datos )
| Número de pieza | MT47H256M4 | |
| Descripción | (MT47HxxxMx) DDR2 SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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DDR2 SDRAM
Features
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• Duplicate output strobe (RDQS) option for x8
configuration
• DLL to align DQ and DQS transitions with CK
• Eight internal banks for concurrent operation
• Programmable CAS Latency (CL): 3 and 4
• Posted CAS additive latency (AL): 0, 1, 2, 3, and 4
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Supports READ burst interrupt by another READ
• Supports WRITE burst interrupt supported by
another WRITE
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
Options
• Configuration
256 Meg x 4 (32 Meg x 4 x 8 banks)
128 Meg x 8 (16 Meg x 8 x 8 banks)
64 Meg x 16 (8 Meg x 16 x 8 banks)
• FBGA Package
92-ball (11mm x 19mm) FBGA
Lead-free
• Timing – Cycle Time
5.0ns @ CL = 4 (DDR2-400)
5.0ns @ CL = 3 (DDR2-400)
3.75ns @ CL = 4 (DDR2-533)
Designation
256M4
128M8
64M16
BT
-5
-5E
-37E
PRELIMINARY‡
1Gb: x4, x8, x16
DDR2 SDRAM
MT47H256M4 – 32 MEG X 4 X 8 BANKS
MT47H128M8 – 16 MEG X 8 X 8 BANKS
MT47H64M16 – 8 MEG X 16 X 8 BANKS
For the latest data sheet, please refer to the Micron Web
site: http://www.micron.com/datasheets
ARCHITECTURE 256 MEG X 4 128 MEG X 8 64 MEG X 16
Configuration
32 Meg x 4 x 8 16 Meg x 8 x 8 8 Meg x 16 x 8
banks
banks
banks
Refresh Count
8K
8K 8K
Row Addressing 16K (A0-A13) 16K (A0-A13) 8K (A0-A12)
Bank
Addressing
8 (BA0 - BA2) 8 (BA0 - BA2) 8 (BA0 - BA2)
Column
Addressing
2K (A0-A9, A11) 1K (A0-A9)
1K (A0-A9)
Table 1: Key Timing Parameters
SPEED
GRADE
-5
-5E
-37E
DATA RATE
(MHz)
CL = 3
–
400
400
CL = 4
400
400
533
tRCD
(ns)
20
15
15
tRP
(ns)
20
15
15
tRC
(ns)
65
55
60
09005aef80fc5fff
1GbDDR2_1.fm - Rev. A 2/04 EN
1 ©2004 Micron Technology, Inc. All rights reserved.
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
1 page  
www.DataSheet4U.com
PRELIMINARY
1Gb: x4, x8, x16
DDR2 SDRAM
Figure 57:
Figure 58:
Figure 59:
Figure 60:
Figure 61:
Figure 62:
Figure 63:
Figure 64:
Figure 65:
Figure 66:
Figure 67:
Figure 68:
Figure 69:
Figure 70:
Figure 71:
Figure 72:
Figure 73:
Figure 74:
Figure 75:
Figure 76:
Figure 77:
ODT Timing for Active or “Fast-Exit” Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
ODT timing for “Slow-Exit” or Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ODT “Turn Off” Timings when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
ODT “Turn-On” Timing when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
ODT “Turn-Off” Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
ODT “Turn On” Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Single-Ended Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Differential Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
AC Input Test Signal Waveform Command/Address pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AC Input Test Signal Waveform for Data with DQS,DQS# (differential) . . . . . . . . . . . . . . . . . . . . . . . .78
AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
AC Input Test Signal Waveform (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Output Slew Rate Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Full Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Full Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Package Drawing (x4,x8,x16 Configurations) 11mm x 19mm “BT” FBGA . . . . . . . . . . . . . . . . . . . . . . .95
09005aef80fc5fff
1GbDDR2LOF.fm - Rev. A 2/04 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
5 Page 
www.DataSheet4U.com
PRELIMINARY
1Gb: x4, x8, x16
DDR2 SDRAM
Table 2: FBGA Ball Descriptions 256 Meg x 4, 128 Meg x 8, 64 Meg x 16
x16 FBGA x4, x8 FBGA
BALL
BALL
ASSIGNMENT ASSIGNMENT SYMBOL
TYPE DESCRIPTION
R8,R3,R7,T2,
T8,T3,T7,U2,
U8,U3,R2,U7,
V2
–
K8,K2,L7,L3,
L1,L9,J1,J9,
F8,F2,G7,G3,
G1,G9,E1,E9
–
–
E7,D8
J7,H8
–
–
– A0–A12
R8,R3,R7,T2,
T8,T3,T7,U2,
U8,U3,R2,U7,
V2,V8
A0–A13
– DQ0–
DQ15
Input
Input
I/O
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for Read/Write
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA2-BA0) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for Read/Write
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA2-BA0) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.
Data Input/Output: Bidirectional data bus for 64 Meg x 16.
K8,K2,L7,L3,
L1,L9,J1,J9
K8,K2,L7,L3
–
–
J7,H8
J3,H2
DQ0–DQ7 I/O Data Input/Output: Bidirectional data bus for 128 Meg x 8.
DQ0–DQ3
UDQS,
UDQS#
LDQS,
LDQS#
DQS,
DQS#
RDQS,
RDQS#
I/O
I/O
I/O
I/O
Output
Data Input/Output: Bidirectional data bus for 256 Meg x 4.
Data Strobe for Upper Byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. UDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
Data Strobe for Lower Byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. LDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
Data Strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data, center
aligned with write data. DQS# is only used when differential data
strobe mode is enabled via the LOAD MODE command.
Redundant Data Strobe for 128 Meg x 8 only. RDQS is enabled/
disabled via the LOAD MODE command to the Extended Mode
Register (EMR). When RDQS is enabled, RDQS is output with read
data only and is ignored during write data. When RDQS is disabled,
pin B3 becomes Data Mask (see DM pin). RDQS# is only used when
RDQS is enabled AND differential data strobe mode is enabled.
09005aef80fc5fff
1GbDDR2_2.fm - Rev. A 2/04 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT47H256M4.PDF ] | |
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