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PDF EM6580 Data sheet ( Hoja de datos )
| Número de pieza | EM6580 | |
| Descripción | Ultra Low Power 8-pin Flash Microcontroller | |
| Fabricantes | EM Microelectronic | |
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MICROELECTRONIC
-
MARIN
SA
EM6580
Ultra Low Power 8-pin Flash Microcontroller
Features
True Low Power:
5.8 µA active mode
3.3 µA standby mode
0.32 µA sleep mode
Large Supply Voltage 2.0 V to 5.5 V
No external component needed
Available in SO-8/14 packages and die
4-bit ADC or 12 levels Supply Voltage Level
Detector (SVLD)
Unique ID code of 52bits + 16bits CRC
Max 4 (5*) outputs with 2 high drive outputs of 10mA
Max. 5 (6*) inputs
Sleep Counter Reset (automatic wake-up from sleep
mode (EM patent))
Flash memory 4096 × 16 bits
RAM 80 × 4 bits
Internal RC oscillator 32kHz – 800kHz
2 clocks per instruction cycle
72 basic instructions
External CPU clock source possible
Watchdog timer (2 sec)
Power-On-Reset with Power-Check on start-up
3 wire serial port , 8 bit, master and slave mode
Universal 10-bit counter, PWM, event counter
Prescaler down to 1 Hz (freq. = 32kHz)
Frequency output 1Hz, 2048 Hz, CPUClk, PWM
6 internal interrupt sources ( 2×10-bit counter, 2×
prescaler, SVLD, Serial Interface)
2 external interrupt sources (port A)
Description
The EM6580 is a low power Flash 4-bit microcontroller
coming in a small 8-pin SO package and working up to
0.4 MIPS. It comes with an integrated 4-bit ADC and 2
high current drive outputs of 10mA and it requires no
external component. It has a sleep counter reset allowing
automatic wake-up from sleep mode. It is designed for use
in battery-operated and field-powered applications
requiring an extended lifetime. A high integration level
make it an ideal choice for cost sensitive applications.
The EM6580 contains the equivalent of 8kB of Flash
memory and a RC oscillator with frequencies between 32
to 800kHz. It also has a power-on reset, watchdog timer,
10 bit up/down counter, PWM and several clock
functions.
Development tools include windows-based simulator
program debugger, assembler and real time emulator.
Figure 1. Architecture
Stable
RC oscillator
32 - 800kHz
Prescaler
10-Bit Univ
Count/Timer
Interrupt
Controller
Flash
4096 x 16Bit
RAM
80 x 4Bit
Core
EM6600
VDD VREG/VPP
Power Supply
Voltage reg.
Power on
Reset
Sleep Counter
Reset
Watchdog
4-bit ADC
SVLD check
Port A
Serial Interface
PA0 PA1 PA2
PA3
Reset
PA4 *PA5
PA1 & PA2:
high current
drive outputs
* PA5 available only
in 14-pin package
and in die
Figure 2. Pin Configuration
SO-8
PA0 1
8 VDD
PA1 2 EM6580 7 VREG/VPP
PA2 3
6 PA4
PA3 4
5 VSS
SO-14
NC 1
14 NC
PA0 2
13 VDD
PA1 3
12 VREG/VPP
PA2 4 EM6580 11 PA5
PA3 5
10 PA4
NC 6
NC 7
9 VSS
8 NC
Typical Applications
Household appliances
Safety and security devices
Automotive controls
Sensor interfaces
Watchdog
Intelligent ADC
Driver (LED, triac)
Copyright © 2005, EM Microelectronic-Marin SA
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EM6580
2. Operating modes
The EM6580 can operate in three different modes of which 2 are low-power dissipation modes (Stand-By and
Sleep). The modes and transitions between them are shown in Figure 5.
1.) Active mode
2.) Stand-By mode
3.) Sleep mode
Figure 4. EM6580 operating mode transitions
START-UP
RC oscilator
running
8 oscillator
periods
RESET
reset synchronizer
clocks active
Power-On-Reset & Power Check Level, ~2.0V
resetPortA
WDreset
PORwPC
PORwPC
PORwPC
POWER-ON
POR static level
Power-Check Active
PORwPC
Reset-pad
WDreset
8 CPU clock
periods
ACTIVE
or running
mode
HALT instruction
interrupt/event
STAND-BY
or HALT
mode
Clocks active
Sleep bit set
SleepResCnt
WakeUp on
Change
SLEEP
Everything stopped
Registers and
RAM keep their value
2.1 ACTIVE Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Leaving the active mode: via the halt instruction to go into standby mode, writing the SLEEP bit to go
into Sleep mode or detecting the reset to go into reset mode.
2.2 STANDBY (Halt) Mode
Executing a HALT instruction puts the EM6580 into standby mode. The voltage regulator, oscillator, watchdog
timer, interrupts, timers and counters are operating. However, the CPU stops since the clock related to
instruction execution stops. Registers, RAM and I/O pins retain their states prior to STANDBY mode.
STANDBY is cancelled by a RESET or an Interrupt request if enabled.
2.3 SLEEP Mode
Writing to the Sleep bit in the RegSysCntl1 register puts the EM6580 in sleep mode. The oscillator stops and
most functions of the EM6580 are inactive. To be able to write to the Sleep bit, the SleepEn bit in
RegSysCntl2 must first be set to "1". In SLEEP mode only the voltage regulator is active to maintain the RAM
data integrity, the peripheral functions are stopped and the CPU is reset.all other functions are in reset state.
SLEEP mode may be cancelled by Wake/Up on change, external reset or by Sleep Reset Counter if any of
them is enabled.
Waking up from sleep mode may takes some time to guarantee stable oscillation. Coming back from sleep
mode puts the EM6681 in reset state and as such reinitializes all registers to their reset value. During sleep
mode and the following start up the EM6580 is in reset state. Waking up from sleep mode clears the Sleep flag
but not the SleepEn bit. Inspecting the SleepEn allows to determine if the EM6580 was powered up (SleepEn
= "0") or woken from sleep mode (SleepEn = "1").
Copyright © 2006, EM Microelectronic-Marin SA
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EM6580
4.4 Sleep Counter Reset
To profit the most from Low Power Sleep Mode and still supervise the circuit surrounding, one can enable the
Sleep Counter Reset which only runs in Sleep mode and periodically wakes up the EM6580. Four (4) different
Wake-Up periods are possible as seen in table below.
Control bits SleepCntDis which is set to default ‘0’by POR enables the Sleep Counter when the circuit goes
into Sleep mode. The SCRsel1, SCRsel0 bits that are used to determine Wake-Up period are in the
RegSleepCR register. To disable the Sleep Counter in Sleep mode SleepCntDis must be set to ‘1’.
Table 4.4.2 Register RegSleepCR
Bit Name
3 NoPullPA[4]
2 SleepCntDis
1 SCRsel1
0 SCRsel0
Reset
0 por
0 por
0 por
0 por
R/W
R/W
R/W
R/W
R/W
Description
Remove pull-up/down from PA[4] input
Disable Sleep Reset Counter when Hi
Selection bit 1 for Sleep RCWake-Up period
Selection bit 0 for Sleep RCWake-Up period
Table 4.4.3 Wake-Up period from Sleep selection
SCRsel1
SCRsel0 Sleep Reset Counter periods
00
1.5 internal low speed RC clock periods
01
15.5 internal low speed RC clock periods
10
127.5 internal low speed RC clock periods
11
1023.5 internal low speed RC clock periods
Refer to table 18.8 or the actual SCR timeout period timings
92H
Sleep Counter Reset (SCR) uses the same prescaler (see chapter 5.3) as the System Clock in Active and
StandBy mode. Prescaler reset is made automatically just before going into Sleep mode if SCR is enable.
This causes the Sleep Reset Counter to have its specified period.
4.5 Wake-Up on Change
By writing the WUchEn[0/5] and/or WUchEn[3/4] bit in RegPaCntl2 registers the PA[0] or PA[5] and/or PA[3]
or PA[4] can generate a reset from sleep on any polarity change on a selected pin. The port selection is
defined with bits IrqPA[0l/5h] and IrqPA[3l/4h]. See chapter 6 and Figure 10 for more details.
4.6 The CPU State after Reset
Reset initializes the CPU as shown in Table 4.6.1 below.
93H
Table 4.6.1 Initial CPU value after Reset.
Name
Bits
Program counter 0
12
Program counter 1
12
Program counter 2
12
Stack pointer
2
Index register
7
Carry flag
1
Zero flag
1
Halt 1
Instruction register
16
Symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
Periphery registers
4 Reg.....
Initial Value
$000 (as a result of Jump 0)
Undefined
Undefined
SP[0] selected
Undefined
Undefined
Undefined
0
Jump 0
See peripheral memory map
Copyright © 2006, EM Microelectronic-Marin SA
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