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PDF AM29DS320G Data sheet ( Hoja de datos )
| Número de pieza | AM29DS320G | |
| Descripción | Simultaneous Operation Flash Memory | |
| Fabricantes | AMD | |
| Logotipo |  |
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Am29DS320G
Data Sheet
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Publication Number 26492 Revision A Amendment +1 Issue Date January 27, 2003
1 page  
ADVANCE INFORMATION
PRODUCT SELECTOR GUIDE
Part Number
Speed Rating
Standard Voltage Range: VCC = 1.8–2.2 V
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
Am29DS320G
70 90
70 90
70 90
30 40
BLOCK DIAGRAM
120
120
120
50
VCC
VSS
A20–A0
Mux
Bank 1 Address
OE# BYTE#
Bank 1
X-Decoder
RY/BY#
A20–A0
RESET#
WE#
CE#
BYTE#
WP#/ACC
DQ15–DQ0
STATE
CONTROL
&
COMMAND
REGISTER
Bank 2 Address
Bank 2
X-Decoder
Status
Control
Bank 3 Address
X-Decoder
Bank 3
A20–A0
Mux
Bank 4 Address
X-Decoder
Bank 4
DQ15–DQ0
Mux
4
Am29DS320G
January 27, 2003
5 Page 
ADVANCE INFORMATION
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC5 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
ICC4 in the DC Characteristics table represents the
reset current. Also refer to AC Characteristics tables
for RESET# timing parameters and to Figure 15 for
the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
10
Am29DS320G
January 27, 2003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM29DS320G.PDF ] | |
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