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PDF DSP56367 Data sheet ( Hoja de datos )
| Número de pieza | DSP56367 | |
| Descripción | 24-Bit Audio Digital Signal Processor | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: DSP56367
Rev. 2.1, 1/2007
DSP56367
24-Bit Audio Digital Signal Processor
1 Overview
This document briefly describes the DSP56367 24-bit
digital signal processor (DSP). The DSP56367 is a
member of the DSP56300 family of programmable
CMOS DSPs. The DSP56367 is targeted to applications
that require digital audio compression/decompression,
sound field processing, acoustic equalization and other
digital audio algorithms. The DSP56367 offers 150
million instructions per second (MIPS) using an internal
150 MHz clock at 1.8 V and 100 million instructions per
second (MIPS) using an internal 100 MHz clock at 1.5 V.
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 Signal/Connection Descriptions . . . . . . . . . . . 2-1
3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
4 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
5 Design Considerations . . . . . . . . . . . . . . . . . . 5-1
A Power Consumption Benchmark . . . . . . . . . . A-1
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2001, 2002, 2003, 2004, 2005, 2006, 2007. All rights reserved.
1 page  
2 Signal/Connection Descriptions
2.1 Signal Groupings
The input and output signals of the DSP56367 are organized into functional groups, which are listed in
Table 2-1 and illustrated in Figure 2-1.
The DSP56367 is operated from a 1.8V supply; however, some of the inputs can tolerate 3.3V. A special
notice for this feature is added to the signal descriptions of those inputs.
Remember, the DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz
clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.3.3V.
Table 2-1 DSP56367 Functional Signal Groupings
Functional Group
Number of
Signals
Detailed
Description
Power (VCC)
Ground (GND)
20 Table 2-2
18 Table 2-3
Clock and PLL
3 Table 2-4
Address bus
Data bus
Port A1
18 Table 2-5
24 Table 2-6
Bus control
10 Table 2-7
Interrupt and mode control
5 Table 2-8
HDI08
Port B2
16 Table 2-9
SHI 5 Table 2-10
ESAI
Port C3
12 Table 2-11
ESAI_1
Port E4
6 Table 2-12
Digital audio transmitter (DAX)
Port D5
2 Table 2-13
Timer
1 Table 2-14
JTAG/OnCE Port
4 Table 2-15
1 Port A is the external memory interface port, including the external address bus, data bus, and control signals.
2 Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.
3 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
4 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
5 Port D signals are the GPIO port signals which are multiplexed with the DAX signals.
Freescale Semiconductor
DSP56367 Technical Data, Rev. 2.1
2-1
5 Page 
Interrupt and Mode Control
Table 2-8 Interrupt and Mode Control
Signal Name
Type
State During
Reset
Signal Description
MODA/IRQA Input
Input
Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects
the initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into the OMR when the RESET signal is deasserted. If the processor
is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor
will exit the stop state.
This input is 3.3V tolerant.
MODB/IRQB Input
Input
Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects
the initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is deasserted.
This input is 3.3V tolerant.
MODC/IRQC Input
Input
Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects
the initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is deasserted.
This input is 3.3V tolerant.
MODD/IRQD Input
Input
Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects
the initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is deasserted.
This input is 3.3V tolerant.
RESET
Input
Input
Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the chip is
placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger
input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably.
When the RESET signal is deasserted, the initial chip operating mode is latched from
the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted
during power up. A stable EXTAL signal must be supplied while RESET is being
asserted.
This input is 3.3V tolerant.
Freescale Semiconductor
DSP56367 Technical Data, Rev. 2.1
2-7
11 Page | ||
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