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PDF MT48LC32M16A2 Data sheet ( Hoja de datos )
| Número de pieza | MT48LC32M16A2 | |
| Descripción | (MT48LCxxMxxA2) SYNCHRONOUS DRAM | |
| Fabricantes | Micron Technology | |
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SYNCHRONOUS
DRAM
ADVANCE‡
512Mb: x4, x8, x16
SDRAM
MT48LC128M4A2 – 32 Meg x 4 x 4 banks
MT48LC64M8A2 – 16 Meg x 8 x 4 banks
MT48LC32M16A2 – 8 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/dramds
FEATURES
• PC100- and PC133-compliant
Pin Assignment (Top View)
• Fully synchronous; all signals registered on positive
edge of system clock
54-Pin TSOP
• Internal pipelined operation; column address can be
changed every clock cycle
x4 x8 x16
• Internal banks for hiding row access/precharge
- - VDD
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
NC DQ0 DQ0
- - VDDQ
NC NC DQ1
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
DQ0 DQ1 DQ2
- - VssQ
NC NC DQ3
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
NC DQ2 DQ4
- - VDDQ
NC NC DQ5
• Single +3.3V ±0.3V power supply
DQ1 DQ3 DQ6
- - VssQ
NC NC DQ7
OPTIONS
MARKING
- - VDD
NC NC DQML
• Configurations
- - WE#
128 Meg x 4 (32 Meg x 4 x 4 banks)
128M4
- - CAS#
- - RAS#
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
3624MMD18a6taSheet4U.co---m
-
-
-
CS#
BA0
BA1
• WRITE Recovery (tWR)
tWR = “2 CLK”1
• Plastic Package – OCPL2
54-pin TSOP II (400 mil)
- - A10
- - A0
A2 - - A1
- - A2
- - A3
TG - - VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
x16 x8 x4
54 Vss - -
53 DQ15 DQ7 NC
52 VssQ - -
51 DQ14 NC NC
50 DQ13 DQ6 DQ3
49 VDDQ - -
48 DQ12 NC NC
47 DQ11 DQ5 NC
46 VssQ - -
45 DQ10 NC NC
44 DQ9 DQ4 DQ2
43 VDDQ - -
42 DQ8 NC NC
41 Vss - -
40 NC - -
39 DQMH DQM DQM
38 CLK - -
37 CKE - -
36 A12 - -
35 A11 - -
34 A9 - -
33 A8 - -
32 A7 - -
31 A6 - -
30 A5 - -
29 A4 - -
28 Vss - -
• Timing (Cycle Time)
7.5ns @ CL = 2 (PC133)
7.5ns @ CL = 3 (PC133)
NOTE: The # symbol indicates signal is active LOW. A dash
-7E (–) indicates x8 and x4 pin function is same as x16
-75 pin function.
• Self Refresh
Standard
Low power
• Operating Temperature
Commercial (0oC to +70oC)
None
L
None
128 Meg x 4
64 Meg x 8
32 Meg x 16
Configuration
32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
Refresh Count
8K
8K
8K
Row Addressing
8K (A0–A12)
8K (A0–A12)
8K (A0–A12)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
Column Addressing 4K (A0–A9, A11, A12) 2K (A0–A9, A11)
1K (A0–A9)
NOTE: 1. Refer to Micron Technical Note TN-48-05.
2. Off-center parting line.
Part Number Example:
MT48LC32M16A2TG-75
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME SETUP HOLD
GRADE FREQUENCY CL = 2* CL = 3* TIME TIME
512Mb SDRAM PART NUMBERS
-7E 143 MHz – 5.4ns 1.5ns 0.8ns
-75 133 MHz – 5.4ns 1.5ns 0.8ns
PART NUMBER
MT48LC128M4A2TG
ARCHITECTURE
128 Meg x 4
-7E 133 MHz 5.4ns – 1.5ns 0.8ns
-75
100 MHz
6ns
– 1.5ns 0.8ns
MT48LC64M8A2TG
MT48LC32M16A2TG
64 Meg x 8
32 Meg x 16
*CL = CAS (READ) latency
DataShee
DataSheet5412UMb.:cx4o, xm8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
DataSheet4 U .com
1 page  
www.DataSheet4U.com
ADVANCE
512Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
64 Meg x 8 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
12
et4U.com
A0-A12,
BA0, BA1
15
ADDRESS
REGISTER
REFRESH 13
COUNTER
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 8)
SENSE AMPLIFIERS
8192
2 DataSheet4U.cDoQMIm/OMGAASTKINLGOGIC
BANK
READ DATA LATCH
CONTROL
WRITE DRIVERS
LOGIC
2
2048
(x8)
COLUMN
DECODER
COLUMN-
ADDRESS
11
11 COUNTER/
LATCH
11
DATA
8 OUTPUT
REGISTER
DATA
8 INPUT
REGISTER
8
DQM
DataShee
DQ0-
DQ7
DataSheet4U.com
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
DataSheet4 U .com
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
5 Page 
www.DataSheet4U.com
COMMANDS
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
ADVANCE
512Mb: x4, x8, x16
SDRAM
following the Operation section; these tables provide
current state/next state information.
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
et4U.com
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM ADDR DQs NOTES
COMMAND INHIBIT (NOP)
HXXXX
X
X
NO OPERATION (NOP)
L HHHX
X
X
ACTIVE (Select bank and activate row)
L L H H X Bank/Row X
3
READ (Select bank and column, and start READ burst)
L H L H L/H8 Bank/Col X
4
WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid 4
BURST TERMINATE
L HH L X
X Active
PRECHARGE (Deactivate row in bank or banks)
L LHLX
Code
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
LL
LL
L HX
X
X
L L X Op-Code X
6, 7
2 DataShee
Write Enable/Output Enable
Write Inhibit/Output High-Z
DataSheet–4U.com– – – L
– – – –H
– Active 8
– High-Z 8
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW.
3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge
feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being
read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
DataSheet4U.com
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
DataSheet4 U .com
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT48LC32M16A2.PDF ] | |
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