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PDF CX51761 Data sheet ( Hoja de datos )
| Número de pieza | CX51761 | |
| Descripción | (CX5000 Series) Structured ASIC | |
| Fabricantes | Chip Express | |
| Logotipo |  |
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DATASHEET
CX5000
0.18um Structured ASIC
Product Description
The 0.18um CX5000 is an ASIC that utilizes the combination of an
advanced metal programmable gate array and optimized EDA system to
implement high performance ASIC designs while reducing application
tooling costs and design turnaround time. ASIC designers using the
CX5000 are able to meet or exceed their design schedules and budgets
without compromising technical objectives.
The CX5000 comprises a family of pre-configured platform masterslices that
contain varying amounts of general-purpose logic, fast memory, advanced
I/Os, clock synthesis and phase management macrocells. When combined with a mix of popular third-
party tools and custom designed point EDA solutions, the CX5000 provides not just gate array hardware,
but also a complete ASIC Platform from which to develop today’s advanced SoC ASICs.
Manufactured in UMC’s 0.18um, 6-layer metal CMOS process, the CX5000 combines the reliability and
quality of an industry-leading silicon foundry, with the high performance, low power consumption and fast
design turnaround time of ChipX Structured ASIC technology. The CX5000 family is very applicable to
cost reduction projects, replacing expensive FPGA devices with low-cost metal programmable
technology. The CX5000 is the first viable “standard cell alternative” ASIC technology, developed in
response to the growing need for cost-effective ASIC implementation capability.
The CX5000 Structured ASIC technology uses just two of the six available metal layers to program the
logic, memory, I/O and clocking of an ASIC design and so eliminates the large costs of the remaining
“fixed” masks. Wafers are manufactured up to Metal 4, where they are held pending completion of the
customer application. Completed chips can be delivered to the customer less than three weeks after sign-
off of the finished design.
ChipX Structured ASIC technology is very similar in concept to FPGA, which makes it easy to use and
familiar to most ASIC and system designers. Using metal interconnect segments rather than SRAM cells
to program the ASIC, CX5000 technology reduces the area of the chip by between 5x and 10x over the
equivalent FPGA and brings performance up to 90% of standard cell design speeds.
Key Features and Benefits
m♦ Structured ASIC architecture
.co♦ Low NRE and start-up costs
U♦ Fast time to production
t4♦ 30K to 1.2M usable ASIC gates
e♦ Up to 2.6M bits of fast block memory
he♦ 2ns access time single-port SRAM, dual-port SRAM and ROM
S♦ Low power consumption (0.06uW/MHz/Gate)
ta♦ 200MHz general core logic operation, 650MHz in constrained clock domains
www.Da© ChipX Inc.
1
CEC034 (9/20/05)
1 page  
www.DataSheet4U.com
CX5000:
0.18um Structured ASIC Product Family
I/O Ring
As shown in Figure 3, the CX5000 I/O ring is comprised of blocks of 8 metal programmable I/O drivers,
16 pads and ESD structures.
Each I/O structure may be split into one simple
input (CMOS or TTL) and one simple output
(CMOS or TTL) to maximize the chip’s signal I/O. In
cases where the cell is configured as a bi-
directional or an advanced single-ended I/O (e.g.,
PCI), the cell supports one signal only; the other
PLL,
Vb & Vref
I/O
Driver
Output
I/O
Driver
I/O
Driver
I/O
Driver
Input
&
VCC
Bidir
GND LVDS
Output
I/O
Driver
LVDS#
pad can be left unconnected or used for power.
Differential I/Os require two I/O structures per
channel and use two pads; the remaining two pads
Customer
Core
are power or no-connect.
omSupported I/O
Figure 3. CX5000 I/O Structure
.cAs shown in Table 4, the CX5000 family supports 676 simple I/O macrocells in addition to a number of
Uadvanced I/Os based on popular industry standards.
www.DataSheet4© ChipX Inc.
5 CEC034 (9/20/05)
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CX51761.PDF ] | |
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