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PDF CXD2932AGA-2 Data sheet ( Hoja de datos )
| Número de pieza | CXD2932AGA-2 | |
| Descripción | GPS Base Band LSI | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2932AGA-2
GPS Base Band LSI
For the availability of this product, please contact the sales office.
Description
The CXD2932AGA-2 is a dedicated LSI for the GPS
144 pin LFLGA (Plastic)
(Global Positioning System) satellite-based position
measurement system.
This LSI contains a 32-bit RISC CPU, satellite
tracking circuit, 2M-bit mask ROM, RAM, UART,
interval timer, and others.
This LSI, used together with the RF LSI, enables the
configuration of a 2-chip system capable of measuring
its position anywhere on the globe.
Absolute Maximum Ratings
Features
• 16-channel GPS receiver capable of
simultaneously receiving 16 satellites
• Supports differential GPS
— Conforms to RTCM SC-104 Ver. 2.1
— Supports DARC
• All-in-view measurement
• Supply voltage VDD VSS – 0.5 to 4.6 V
• Input voltage
VI VSS – 0.5 to VDD + 0.5 V
• Output voltage VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature
Topr –40 to +85 °C
• Storage temperature
Tstg
–50 to +150
°C
• Timer supporting GPS time
• 32-bit RISC CPU
• 256K-byte program ROM
• 40K-byte RAM
• Power management function
Recommended Operating Conditions
• Supply voltage VDD
3.0 to 3.6
• Operating temperature
Topr –40 to +85
V
°C
• 1PPS supported
• 2-channel UART
• 4-channel interval timer
• 16-bit general-purpose I/O port
• 12-bit successive approximation system A/D
Input/Output Pin Capacitance
• Input capacitance CIN
9 (Max.)
• Output capacitance COUT 11 (Max.)
• I/O capacitance
CI/O
11 (Max.)
pF
pF
pF
converter (4-channel analog switch)
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E03202A37
1 page  
Pin Description
Pin
No.
Symbol
1 VSS9
2 PORT2
3 PORT3
4 PORT4
5 PORT5
6 PORT6
7 PORT7
8 VDD9
9 PORT8
10 PORT9
11 PORT10
12 PORT11
13 PORT12
14 PORT13
15 VSS10
16 PORT14
17 PORT15
18 TXD0
19 RXD0
20 TXD1
21 RXD1
22 VDD10
23 IFI
24 IFO
25 TEST0
26 TEST1
27 CCKI
28 CCKO
29 VSS11
30 REFCK
31 TRST
32 TCK
33 TDI
34 TDO
35 TMS
36 VDD11
37 AVD2
I/O Description
— VSS
I/O/Z I/O port 2 (See the Application Circuit for setting.)
I/O/Z I/O port 3 (See the Application Circuit for setting.)
I/O/Z I/O port 4 (See the Application Circuit for setting.)
I/O/Z I/O port 5 (See the Application Circuit for setting.)
I/O/Z I/O port 6 (See the Application Circuit for setting.)
I/O/Z I/O port 7 (See the Application Circuit for setting.)
— VDD
I/O/Z I/O port 8 (See the Application Circuit for setting.)
I/O/Z I/O port 9 (See the Application Circuit for setting.)
I/O/Z I/O port 10 (See the Application Circuit for setting.)
I/O/Z I/O port 11 (See the Application Circuit for setting.)
I/O/Z I/O port 12 (See the Application Circuit for setting.)
I/O/Z I/O port 13 (See the Application Circuit for setting.)
— VSS
I/O/Z I/O port 14
I/O/Z I/O port 15
O/Z UART transmission data (CH0)
I UART reception data (CH0)
O/Z UART transmission data (CH1)
I UART reception data (CH1)
— VDD
I
IF signal binary conversion circuit
O
I Test (Low level fixed)
I Test (Low level fixed)
I
Timer oscillation circuit (32.768kHz ± 100ppm)
O
— VSS
I Test (Low level fixed)
I Test (Open)
I Test (Open)
I Test (Open)
O/Z Test
I Test (Open)
— VDD
— A/D converter VDD
–5–
CXD2932AGA-2
5 Page 
CXD2932AGA-2
AC Characteristics
(1) External Memory Read Timing
(VDD = 3.0 to 3.6V, CL = 40pF, Topr = –40 to +85°C, CPU clock = 18.4MIPS)
Item
Read cycle time (0WAIT)∗1
Read cycle time (1WAIT)∗1
Read cycle time (2WAIT)∗1
Read cycle time (3WAIT)∗1
Symbol
Min.
Typ.
Max.
Unit
Trcy0
54 ns
Trcy1
108 ns
Trcy2
162 ns
Trcy3
216 ns
Address delay time
Tca 0
4 ns
Read signal fall delay time
Tcfo 2
10 ns
Read signal rise delay time
Tcro
2
10 ns
Read data setup time
Tds 22
ns
Read data hold time
Tdh
0 ns
∗1 0WAIT (normal), 1 to 3WAIT (settable according to the program)
XCS
EA
XOE
Tsys∗ (1 to 4)
Trcy0 to 3
Tca
Tsys
Tca
Tcfo Tcro
ED
∗ Tsys: CPU clock cycle
Tds
Tdh
– 11 –
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| PDF Descargar | [ Datasheet CXD2932AGA-2.PDF ] | |
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