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PDF SII154 Data sheet ( Hoja de datos )
| Número de pieza | SII154 | |
| Descripción | Display Ranging | |
| Fabricantes | Silicon Image | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SII154 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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.comSiI 154
t4UPreliminary Data Sheet
eeGeneral Description
hThe SiI154 transmitter uses PanelLink® Digital
Stechnology to support displays ranging from VGA to
taSXGA resolutions (25-112MPps) in a single link
ainterface. The SiI154 transmitter has a highly flexible
.Dinterface with 12-bit (½ pixel) or 24-bit 1 pixel/clock
input for true color (16.7 million) support. In 24-bit
wmode, the data may be latched on the positive or
w negative edge of the clock. In 12-bit mode, multiple
w clocking options exist: with a single clock, data will be
clocked on the falling and the rising edge; with dual
mclocks data can be clocked on either the falling edge
oof the rising edge of both clocks.
.cPanelLink Digital technology simplifies PC design by
resolving many of the system level issues associated
with high-speed digital design, providing the system
Udesigner with a digital interface solution that is
quicker to market and lower in cost.
t4SiI 154 Pin Diagram
Features
• Scaleable Bandwidth: 25-112 Mega-pixels/sec
(VGA to SXGA)
• Flexible Panel Interface: 12-bit (½ pixel) or 24-bit 1
pixel/clock inputs
• I2C Slave Programming Interface
• Low Voltage Interface: 1.0 to 1.8V capable
• Receiver Detection: Supports Hot Plug Detection
through RxDetect feature
• De-skewing Option: varies clock to data timing
• High Inter-Pair Skew Tolerance: 1 full input clock
cycle (9 ns at 108MHz)
• Low Power: 3.3V core operation and power down
mode
• Cable Distance Support: over 5m with twisted
pair, fiber-optics ready
• Standards Compliant with DVI 1.0 (DVI is
backwards compliant with VESA® P&DTM and
DFP)
taSheeVCC
RESERVED
aDKEN
D23
.DD22
D21
D20
w SiI 154D19
wD18
D17
w omD16
.cD15
UD14
t4D13
eD12
www.DataSheGND
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
64-Pin TQFP
(Top View)
Figure 1. SiI 154 Pin Diagram
16 GND
15 BSEL/SCL
14 DSEL/SDA
13 ISEL/RST
12 VCC
11 MSEN
10 PD
9 EDGE/HTPLG
8 CTL1/A1/DK1
7 CTL2/A2/DK2
6 CTL3/A3/DK3
5 VSYNC
4 HSYNC
3 VREF
2 DE
1 VCC
1 page  
Silicon Image, Inc.
Input Timing Diagrams
SiI154
TCIH
VIH VIH
TCIP
VIL VIL
TCIL
Figure 2. Clock Cycle/High/Low Times
SiI/DS-0010-D
SLHT
SHLT
80% VOD
20% VOD
Figure 3. Differential Transition Times
IDCK+/IDCK-
D[23:0], DE,
HSYNC,VSYNC,
VIH
TSIDF
VIH
VIL
VIL
TSIDR
VIL
THIDF
VIH
VIH
VIL
THIDR
Figure 4. Control and Single-Edge-Data Setup/Hold Times to IDCK+/IDCK-
Revision 0.94
5 Subject to Change without Notice
5 Page 
Silicon Image, Inc.
SiI154
SiI/DS-0010-D
Configuration/Programming Pins
Pin Name
Pin # Type Description
ISEL/RST 13 In I2C Interface Select. If HIGH, then the I2C interface is active. If LOW, the I2C is
inactive and the chip configuration is read from the configuration strapping pins.
This pin also acts as an asynchronous reset to the I2C interface controller. The
reset is active when this input is held LOW.
Note: When then the I2C interface is active, DKEN must be set high.
BSEL/SCL
15
DSEL/SDA
14
EDGE/HTPLG 9
In Input bus select / I2C clock. This pin is an open collector input. If I2C bus is
enabled (ISEL = HIGH), then this pin is the I2C clock input. If the I2C is disabled
(ISEL = LOW), then this pin selects the input bus width.
Input Bus Select :
HIGH selects 24-bit input mode
LOW selects 12-bit input mode
In Dual edge clock select / I2C Data. This pin is an open collector input. If I2C bus is
enabled (ISEL = HIGH), then this pin is the I2C data line. If the I2C bus is disabled
(ISEL = LOW), then this pin selects whether dual edge clocking is used.
Dual edge clock select :
When HIGH, IDCK+ latches input data on both falling and rising clock
edges.
When LOW, IDCK+/IDCK- latches input data on only falling or rising
clock edges. See the differences between 12 and 24 bit mode below:
In 12-bit mode (BSEL = LOW):
If HIGH (dual edge), IDCK+ is used to latch data on both falling and
rising edges.
If LOW (single edge), IDCK+ latches 1st half data and IDCK- latches 2nd
half data.
In 24-bit mode (BSEL = HIGH):
DSEL must be set LOW
In Edge select / Hot Plug input. If the I2C bus is enabled (ISEL = HIGH), then this pin
is used to monitor the “Hot Plug” detect signal (Please refer to the DVITM or VESA®
P&DTM and DFP standards). NOTE: This Input is ONLY 3.3V tolerant and has no
internal debouncer circuit.
If I2C bus is disabled (ISEL = LOW), then this pin selects the clock edge that will
latch the data. How the EDGE setting works depends on whether dual or single
edge latching is selected :
Dual Edge Mode (DSEL = HIGH)
EDGE = LOW,the primary edge (first/even latch edge after DE is
asserted) is the falling edge.
EDGE = HIGH,the primary edge (first/odd latch edge after DE is
asserted) is the rising edge.
Note:
In dual edge mode, the control signals HS and VS are only latched on
the secondary clock edge.
DKEN
Single Edge Mode (DSEL = LOW)
EDGE = LOW, the falling edge of the clock is used to latch data.
EDGE = HIGH, the rising edge of the clock is used to latch data.
35 In De-Skewing enable.
This pin determines whether the de-skewing increments are to be read in through
the DK[3:1] pins or the General Purpose Input CTL[3:1] are active.
DKEN = LOW, ISEL = LOW
Default de-skewing setting is used and General Purpose Input
CTL[3:1] are active.
DKEN = HIGH, ISEL = LOW
DK[3:1] is used as the de-skewing setting. The de-skewing
increments are TSTEP
DKEN = HIGH, ISEL = HIGH
If I2C bus is enabled (ISEL = HIGH), then DKEN must be set high,
DK[3:1] are ignored and the de-skewing increments are selected through
the I2C interface (see the I2C register definitions).
Revision 0.94
11 Subject to Change without Notice
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SII154.PDF ] | |
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