|
|
PDF MT46V128M8 Data sheet ( Hoja de datos )
| Número de pieza | MT46V128M8 | |
| Descripción | (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT46V128M8 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
m 1Gb: x4, x8, x16 DDR SDRAM
o Features
Double eDeat4tUa.c Rate (DDR) SDRAMMT46V256M4 – 64 Meg x 4 x 4 banks
ShMT46V128M8 – 32 Meg x 8 x 4 banks
ataMT46V64M16 – 16 Meg x 16 x 4 banks
.DFor the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets
wwFeatures
w• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
mVDD = VDDQ = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
oreceived with data, i.e., source-synchronous data
.ccapture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
U• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
t4• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
e• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
e• Data mask (DM) for masking write data (x16 has two
–one per byte)
h• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
S• Longer lead TSOP for improved reliability (OCPL)
ta• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)
Options
• Configuration
256 Meg x 4 (64 Meg x 4 x 4 banks)
128 Meg x 8 (32 Meg x 8 x 4 banks)
64 Meg x 16 (16 Meg x 16 x 4 banks)1
• Plastic Package – OCPL
66-pin TSOP(400 mil width, 0.65mm
pin pitch)
66-pin TSOP lead-free (400 mil width,
0.65mm pin pitch)
• Timing – Cycle Time
7.5ns @ CL = 2.5 (DDR266B)2
6ns @ CL = 2.5 (DDR333B)2
5ns @ CL = 3 (DDR400B)
• Temperature Rating
Commercial (0°C to +70°C)
• Design Revision
Marking
256M4
128M8
64M16
TG
P
-75
-6T
-5B
None
:A
Notes:1. Contact Micron for product availability.
2. See Table 3 on page 2 for module compatibil-
ity.
aTable 1: Addressing Configuration
.DConfiguration
wRefresh Count
Row Addressing
wBank Addressing
mColumn Addressing
256 Meg x 4
64 Meg x 4 x 4 banks
8K
16K (A0–A13)
4(BA0,BA1)
4K(A0–A9, A11, A12)
128 Meg x 8
32 Meg x 8 x 4 banks
8K
16K (A0–A13)
4(BA0,BA1)
2K(A0–A9, A11)
64 Meg x 16
16 Meg x 16 x 4 banks
8K
16K (A0–A13)
4(BA0,BA1)
1K(A0–A9)
w U.coTable 2:
Key Timing Parameters
CL = CAS (read) latency; data out window is minimum clock rate at CL = 2.5
eet4Speed Grade
Sh-75
ta-6T
a-5B
CL = 2
100 MHz
133 MHz
133 MHz
Clock Rate
CL = 2.5
133 MHz
167 MHz
167 MHz
CL = 3
NA
NA
200 MHz
Data-Out
Window
2.5ns
2.0ns
1.6ns
Access
Window
±0.75ns
±0.70ns
±0.70ns
DQS–DQ
Skew
+0.50ns
+0.45ns
+0.40ns
w.DPDF: 09005aef80a2f898/Source: 09005aef80a2f8ae
w1gbBDDRx4x8x16_1.fm - Rev. D 8/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
wProducts and specifications discussed herein are subject to change by Micron without notice.
1 page  
1Gb: x4, x8, x16 DDR SDRAM
List of Figures
List of Figures
Figure 1: 1Gb DDR SDRAM Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 2: Functional Block Diagram 256 Meg x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3: Functional Block Diagram 128 Meg x8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4: Functional Block Diagram 64 Meg x16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 5: Pin Assignment (Top View) 66-pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 7: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 9: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 10: Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK≤3 . . . . . . . . . . . . . . . . .25
Figure 11: READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 12: READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 13: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 14: Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 15: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 16: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 17: READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 18: READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 19: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 20: WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 21: Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 22: Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 23: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 24: WRITE to READ - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 25: WRITE to READ - Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 26: WRITE to READ - Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 27: WRITE to PRECHARGE - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 28: WRITE to Precharge – Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 29: WRITE to PRECHARGE Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 30: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 31: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 32: Input Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 33: SSTL_2 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 34: Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 35: Full Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 36: Full Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 37: Reduced Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 38: Reduced Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 39: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . .73
Figure 40: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 41: Data Output Timing – tAC and tDQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 42: Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 43: Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Figure 44: Initialize and Load Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 45: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 46: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 47: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 48: Bank Read - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 49: Bank Read - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Figure 50: Bank Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 51: Bank Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 52: Write - DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 53: 66-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
PDF: 09005aef80a2f898/Source: 09005aef80a2f8ae
1gbDDRx4x8x16LOF.fm - Rev. D 8/05 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
5 Page 
1Gb: x4, x8, x16 DDR SDRAM
Table 4: Pin Descriptions (Continued)
TSOP
Numbers
2, 4, 5,
7, 8, 10,
11, 13, 54,
56, 57, 59,
60, 62, 63,
65
14, 25, 43, 53
Symbol
DQ0–DQ2
DQ3–DQ5
DQ6–DQ8
DQ9–DQ11
DQ12–DQ14
DQ15
NC
2, 5, 8,
11, 56, 59,
62, 65
4, 7, 10, 13, 14,
16, 20, 25, 43,
53, 54, 57, 60,
63,
5, 11, 56,
62
4, 7, 10, 13, 14,
16, 20, 25, 43,
53, 54, 57, 60,
63
2, 8, 59, 65
DQ0–DQ2
DQ3–DQ5
DQ6, DQ7
NC
DQ0–DQ2
DQ3
NC
NF
51
16
51
19, 50
3, 9, 15, 55, 61
DQS
LDQS
UDQS
DNU
VDDQ
6, 12, 52, 58, 64
1, 18, 33
34, 48, 66
49
VSSQ
VDD
VSS
VREF
Type
I/O
Description
Data Input/Output: Data bus for x16
– No Connect for x16
These pins should be left unconnected.
I/O Data Input/Output: Data bus for x8
– No Connect for x8
These pins should be left unconnected.
I/O Data Input/Output: Data bus for x4
– No Connect for x4
These pins should be left unconnected.
–
I/O
–
Supply
Supply
Supply
Supply
Supply
No Function for x4
These pins should be left unconnected.
Data Strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, centered in write data. It is used to capture data.
For the x16, LDQS is DQS for DQ0–DQ7 and UDQS is DQS for DQ8–DQ15.
Pin 16 (E7) is NC on x4 and x8.
Do Not Use: Must float to minimize noise on VREF.
DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved noise
immunity.
DQ Ground. Isolated on the die for improved noise immunity.
Power Supply: +2.5V ±0.2V.
Ground.
SSTL_2 reference voltage.
PDF: 09005aef80a2f898/Source: 09005aef80a2f8ae
1gbDDRx4x8x16_2.fm - Rev. D 8/05 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT46V128M8.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT46V128M4 | Double Data Rate (DDR) SDRAM | Micron Technology |
| MT46V128M8 | (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM | Micron Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |