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PDF MT46V32M16 Data sheet ( Hoja de datos )
| Número de pieza | MT46V32M16 | |
| Descripción | Double Data Rate (DDR) SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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512Mb: x4, x8, x16 DDR SDRAM
Features
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
Features
•
VDD =
VDD
2.5V ±0.2V, VDDQ =
= 2.6V ±0.1V, VDDQ
2.5V ±0.2V
= 2.6V ±0.1V
(DDR400)1
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh
– 64ms, 8192-cycle
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)
Options
Marking
• Configuration
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
128M4
64M8
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
• Plastic package
32M16
– 66-pin TSOP
TG
– 66-pin TSOP (Pb-free)
– 60-ball FBGA (10mm x 12.5mm)
– 60-ball FBGA (10mm x 12.5mm) (Pb-free)
– 60-ball FBGA (8mm x 12.5mm)
– 60-ball FBGA (8mm x 12.5mm) (Pb-free)
• Timing – cycle time
P
FN2
BN2
CV3
CY3
– 5ns @ CL = 3 (DDR400)
– 6ns @ CL = 2.5 (DDR333) (FBGA only)
– 6ns @ CL = 2.5 (DDR333) (TSOP only)
-5B
-62
-6T2
• Self refresh
– Standard
None
– Low-power self refresh
• Temperature rating
L
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
None
IT
• Revision
– x4, x8, x16
– x4, x8, x16
:F
:J
Notes: 1. DDR400 devices operating at < DDR333
conditions can use VDD/VDDQ = 2.5V +0.2V.
2. Available only on Revision F.
3. Available only on Revision J.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3
Speed
Grade
-5B
-6
6T
-75E/-75Z
-75
CL = 2
133
133
133
133
100
Clock Rate (MHz)
CL = 2.5
167
167
167
133
133
CL = 3
200
n/a
n/a
n/a
n/a
Data-Out
Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
Access
Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
DQS–DQ
Skew
0.40ns
0.40ns
0.45ns
0.50ns
0.50ns
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
1 page  
512Mb: x4, x8, x16 DDR SDRAM
Functional Description
Functional Description
The DDR SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture with an inter-
face designed to transfer two data words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-
cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-
half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The x16 offering has two data strobes,
one for the lower byte and one for the upper byte.
The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which may then
be followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8
locations. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All
inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs
are SSTL_2, Class II compatible.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper
byte. For the lower byte (DQ[7:0]) DM refers to LDM and DQS refers to LDQS. For the
upper byte (DQ[15:8]) DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document and any page or
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
5 Page 
512Mb: x4, x8, x16 DDR SDRAM
Pin and Ball Assignments and Descriptions
Table 4: Pin and Ball Descriptions (continued)
FBGA
Numbers
E3
E7
E3
TSOP
Numbers
51
16
51
F8, M7, A7
B2, D2, C8,
E8, A9
F1
A3, F2, M3
A1, C2, E2,
B8, D8
–
B1, B9, C1,
C9, D1, D9,
E1, E7, E9,
F7
B1, B9, C1,
C9, D1, D9,
E1, E7, E9,
F7
A2, A8, C3,
C7
F9
1, 18, 33
3, 9, 15, 55,
61
49
34, 48, 66
6, 12, 52,
58, 64
14, 17, 25,
43, 53
4, 7, 10,
13, 14, 16,
17, 20, 25,
43, 53, 54,
57, 60, 63
4, 7, 10, 13,
14, 16, 17,
20, 25, 43,
53, 54, 57,
60, 63
2, 8, 59, 65
19, 50
Symbol
DQS
LDQS
UDQS
VDD
VDDQ
VREF
VSS
VSSQ
NC
NC
NC
NF
DNU
Type Description
I/O Data strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, centered in write data. It is used to capture data.
For the x16, LDQS is DQS for DQ[7:0] and UDQS is DQS for DQ[15:8]. Pin
16 (E7) is NC on x4 and x8.
Supply Power supply: 2.5V ±0.2V. (2.6V ±0.1V for DDR400).
Supply DQ power supply: 2.5V ±0.2V (2.6V ±0.1V for DDR400). Isolated on the
die for improved noise immunity.
Supply SSTL_2 reference voltage.
Supply Ground.
Supply DQ ground: Isolated on the die for improved noise immunity.
– No connect for x16: These pins should be left unconnected.
– No connect for x8: These pins should be left unconnected.
– No connect for x4: These pins should be left unconnected.
– No function for x4: These pins should be left unconnected.
– Do not use: Must float to minimize noise on VREF.
Table 5:
Reserved NC Pin and Ball Descriptions
NC pins not listed may also be reserved for other uses; this table defines NC pins of importance
TSOP
Numbers
17
Symbol
A13
Type
Input
Description
Address input A13 for 1Gb devices.
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
11 Page | ||
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| PDF Descargar | [ Datasheet MT46V32M16.PDF ] | |
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