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PDF CYD09S72V Data sheet ( Hoja de datos )
| Número de pieza | CYD09S72V | |
| Descripción | (CYDxxS72V) FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
FLEx72™ 3.3V 64K/128K/256K x 72
Synchronous Dual-Port RAM
Features
Functional Description
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined operation
• Family of 4-Mbit, 9-Mbit and 18-Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 484-ball FBGA (1 mm pitch)
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
• Seamless Migration to Next Generation Dual Port
Family
The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit
pipelined, synchronous, true dual-port static RAMs that are
high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location
in memory. The result of writing to the same location by more
than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal set-up and
hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S72V device have limited features. Please see
“Address Counter and Mask Register Operations[16]” on
page 6 for details.
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
Seamless Migration to Next Generation Dual Port Family
Cypress offers a migration path for all devices to the
next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details
4-Mbit
(64K x 72)
CYD04S72V
167
4.0
225
484-ball FBGA
23mm x 23mm
9-Mbit
(128K x 72)
CYD09S72V
167
4.0
270
484-ball FBGA
23mm x 23mm
18-Mbit
(256K x 72)
CYD18S72V
133
5.0
410
484-ball FBGA
23mm x 23mm
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06069 Rev. *D
Revised June 23, 2004
1 page  
PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Pin Definitions (continued)
Left Port
Right Port
TDI
TCK
TDO
VSS
VCORE
VTTL
Description
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK.
TDO is normally three-stated except when captured data is shifted out of the
JTAG TAP.
Ground Inputs.
Core Power Supply.
LVTTL Power Supply.
Master Reset
The FLEx72 family devices undergo a complete reset by
taking the MRST input LOW. MRST input can switch
asynchronously to the clocks. MRST initializes the internal
burst counters to zero, and the counter mask registers to all
ones (completely unmasked). MRST also forces the mailbox
interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the FLEx72 family
devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports using 18Mbit
device as an example. The highest memory location, 3FFFF
is the mailbox for the right port and 3FFFE is the mailbox for
the left port. Table 2.shows that in order to set the INTR flag, a
Table 2. Interrupt Operation Example [1, 11, 12, 13]
write operation by the left port to address 3FFFF will assert
INTR LOW. At least one byte has to be active for a write to
generate an interrupt. A valid Read of the 3FFFF location by
the right port will reset INTR HIGH. At least one byte has to be
active in order for a read to reset the interrupt. When one port
writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Left Port
Right Port
Function
Set Right INTR Flag
R/WL
L
CEL
L
A0L–17L
3FFFF
INTL
X
R/WR
X
CER
X
A0R–17R
X
INTR
L
Reset Right INTR Flag
X
X
X
X
H
L 3FFFF H
Set Left INTL Flag
X
X
X
L
L
L 3FFFE X
Reset Left INTL Flag
H
L 3FFFE H
X
X
X
X
Note:
11. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of
the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
12. OE is “Don’t Care” for mailbox operation.
13. At least one of BE0 or BE7 must be LOW.
Document #: 38-06069 Rev. *D
Page 5 of 26
5 Page 
PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Maximum Ratings [21]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Supply Voltage to Ground Potential .............. –0.5V to + 4.6V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VDD + 0.5V
DC Input Voltage .............................. –0.5V to VDD + 0.5V[22]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2000V
(JEDEC JESD22-A114-2000B)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VDD
3.3V
± 165 mV
3.3V
± 165 mV
VCORE
1.8V
± 100 mV
1.8V
± 100mV
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
IOZ
IIX1
IIX2
ICC
ISB1
ISB2
ISB3
ISB4
ISB5
ICORE
Description
Part No.
Output
mA)
HIGH
Voltage
(VDD
=
Min.,
IOH=
–4.0
Output
mA)
LOW
Voltage
(VDD
=
Min.,
IOL=
+4.0
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Input Leakage Current Except TDI, TMS,
MRST
Input Leakage Current TDI, TMS, MRST
Operating Current
(OVuDtDpu=tsMDaixs.a,IbOleUdT = 0 mA),
CYD04S72V
CYD09S72V
CYD18S72V
Standby Current
(Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
Standby Current
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
Standby Current (Both Ports
VCDMDO–S0L.2eVve, lf)=C0EL and CER ≥
Standby Current
(One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
Operating Current
(VDDIO = Max,Iout=0mA,f=0)
Outputs Disabled
CYD04S72V
CYD09S72V
CYD04S72V
CYD09S72V
CYD04S72V
CYD09S72V
CYD04S72V
CYD09S72V
CYD18S72V
Core Operating Current for
= 0 mA), Outputs Disabled
(VDD
=
Max.,IOUT
Min.
2.4
2.0
–10
–10
–0.1
-167
Typ.
225
90
160
55
160
0
Max.
0.4
0.8
10
10
1.0
300
115
210
75
210
0
Min.
2.4
2.0
–10
–10
–0.1
-133
Typ.
225
410
90
160
55
160
0
Max.
0.4
0.8
10
10
1.0
300
580
115
210
75
210
75
0
Min.
2.4
-100
Typ
2.0
-10
-10
-0.1
315
0
Max Unit
V
0.4 V
V
0.8 V
10 µA
10 µA
1.0 mA
mA
450 mA
mA
mA
mA
mA
75 mA
0 mA
Capacitance [23]
Part#
Parameter
Description
Test Conditions
CYD04S72V
CYD09S72V
CIN
COUT
Input Capacitance
Output Capacitance
TVADD=
25°C, f
= 3.3V
=
1
MHz,
CYD18S72V CIN
Input Capacitance
COUT
Output Capacitance
Note:
21. The voltage on any input or I/O pin can not exceed the power pin during power-up.
22. Pulse width < 20 ns.
23. COUT also references CI/O
Max.
20
10[24]
40
20
Unit
pF
pF
pF
pF
Document #: 38-06069 Rev. *D
Page 11 of 26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet CYD09S72V.PDF ] | |
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