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PDF MB15A02 Data sheet ( Hoja de datos )
| Número de pieza | MB15A02 | |
| Descripción | Low Power Serial Input PLL Synthesizer With 1.1ghz Prescaler | |
| Fabricantes | Fujitsu Microelectronics | |
| Logotipo |  |
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DS04–21321–1aE
DATA SHEET
MB15A02 ASSP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
LOW POWER SERIAL INPUT PLL
SYNTHESIZER WITH 1.1GHZ PRESCALER
The Fujitsu MB15A02, utilizing Bi-CMOS technology, is a single chip serial input
PLL synthesizer with pulse-swallow function.
The MB15A02 contains a 1.1GHz two modulus prescaler that can select either a
64/65 or 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit
latch, programmable reference divider (binary 14-bit programmable reference
counter), 1-bit switch counter, phase comparator with phase reverse function,
charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, and programmable
divider (binary 7-bit swallow counter and binary 11-bit programmable counter).
It operates supply voltage of 5V typ. and achieves very low supply current of 7mA
typ. realized through the use of Fujitsu Advanced Process Technology.
PLASTIC PACKAGE
FPT-16P–M05
• High operating frequency: fIN MAX=1.1GHz (PIN MIN=–10dBm)
• Pulse swallow function: 64/65 or 128/129
• Low supply current: ICC=7mA typ.
• Serial input 18-bit programmable divider consisting of:
– Binary 7-bit swallow counter: 0 to 127
– Binary 11-bit programmable counter: 16 to 2,047
• Serial input 15-bit programmable reference divider consisting of:
– Binary 14-bit programmable reference counter: 6 to 16,383
– 1-bit switch counter (SW) sets divide ratio of prescaler
• Two types of phase detector output
– On-chip charge pump (Bipolar type)
– Output for external charge pump
PLASTIC PACKAGE
FPT-16P–M06
• Wide operating temperature: –40°C to +85°C
• 16–pin Plastic SOP Package
16–pin and 20–pin Plastic SSOP Packages
w ABSOLUTE MAXIMUM RATINGS (See NOTE)
w Rating Symbol
Rating
w.Power Supply Voltage
VCC
VP
–0.5 to +7.0
VCC to 8.0
DOutput Voltage
VOUT –0.5 to VCC +0.5
atOpen-drain Voltage
VOOP
–0.5 to 6.0
aOutput Current IOUT ±10
ShStorage Temperature
TSTG
–55 to +125
Unit
V
V
V
V
mA
°C
Remark
∅P pin
eet4NOTE:
Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
www.UD.caomtaSheet4U.com©Copyright
FUJITSU LIMITED and FUJITSUMICROELECTRONICS, INC.
PLASTIC PACKAGE
FPT-20P–M03
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. How-
ever, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated
voltages to this high impedance circuit.
1
1 page  
MB15A02
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift register and when load enable pin is high level or open, stored
data is transferred into latch according to the control bit.
Control data ”H” data is transferred into 15-bit latch.
Control data ”L” data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit programmable reference counter. Serial 16-bit
data format is shown below.
Direction of data shift
Control bit
Divide ratio of prescaler setting bit
LSB MSB
CS S S S S S S S S S S S S S S
1 2 3 4 5 6 7 8 9 10 11 12 13 14 W
Divide ratio of programmable reference counter setting bit
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide S S S S S S S S S S S S S S
Ratio
R 14 13 12 11 10 9 8 7 6 5 4 3 2 1
6 0 00 0 0 0 0 0 0 0 0 1 1 0
7 00000000000111
• ••••••••••••••
16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1
NOTES: Divide ratio less than 6 is prohibited.
Divide ratio: 6 to 16,383
SW: This bit selects divide ratio of prescaler.
SW=H : 64/65
SW=L : 128/129
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets at high level).
Start data input with MSB first.
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown following page.
5
5 Page 
TYPICAL APPLICATION EXAMPLE
VPX(6V)
10k
12k
12k
10k
LPF
Charge Pump
Selection
(Internal or
external)
MB15A02
VCO
OUTPUT
FROM
CONTROLLER
∅R ∅P fOUT NC FC LE Data Clock 47k 47k
16 15 14 13 12
11 10
9
MB15A02 (SOP/SSOP 16–pin)
123
OSCIN OSCOUT Vp
45
VCC
DO
67
GND LD
8
fin
X’tal 1000p
C1 C2
0.1µ 0.1µ
LOCK DET.
VPX : 6V max.
VP : When internal charge pump is not used, VP pin needs to be connected to VCC.
C1, C2: Depends on crystal oscillator
LE,FC : With internal pull up resistor
∅P : Open drain output
∅R : CMOS output
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MB15A02.PDF ] | |
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