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PDF ST5481 Data sheet ( Hoja de datos )
| Número de pieza | ST5481 | |
| Descripción | L.O.U.I.S - LOW COST USB ISDN SOLUTION | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ST5481 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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ST5481
L.O.U.I.S - LOW COST USB ISDN SOLUTION
PRODUCT PREVIEW
HARDWARE FEATURES
S/T ISDN Interface
s SUPPORTS OSI LEVEL 1 IN CONFOR-
MANCE WITH UIT-T I.430 FOR BASIC
ACCESS AT S AND T INTERFACES (ETSI
300012/ANSI T1.605)
s LINE INTERFACE TRANSFORMER DIRECT
DRIVE
s FULL-DUPLEX TRANSMISSION AT 192KBps
ON SEPARATE TRANSMIT AND RECEIVE
TWISTED PAIRS USING ALTERNATE MARK
INVERSION (AMI) LINE CODING
s 2 B CHANNELS AT 64KBps EACH PLUS 1 D
CHANNEL AT 16KBps
s ALL I.430 WIRING CONFIGURATIONS
SUPPORTED INCLUDING PASSIVE BUS
FOR TE’S DISTRIBUTED POINT TO POINT
AND POINT TO MULTIPOINT
s MULTIFRAME SUPPORT
s ANALOG PART: INCLUDED WITH
ADAPTIVE DETECTION THRESHOLD AND
EQUALIZER
USB Interface
s USB 1.0 SPECIFICATION FULL COMPLI-
ANCE, 1.1 SPECIFICATION COMPATI-
BILITY (1.1 POWER MANAGEMENT COM-
PLIANCE), 12 MBps FULL SPEED
s ON-CHIP USB TRANSCEIVER WITH
DIGITAL PLL
s 6 ISOCHRONOUS ENDPOINTS FOR B1,
B2, D CHANNELS DATA.INTERRUPT
ENDPOINT FOR I430
s ISDN PROTOCOL AND DATA.CONTROL
ENDPOINT FOR USB STANDARD PLUS
VENDOR SPECIFIC REQUEST
s COMMUNICATION DEVICE CLASS AND
VENDOR REQUESTS
s BUS OR SELF POWERED APPLICATION
(PIN PROGRAMMABLE)
s ONNOW POWER MANAGEMENT (D0,D2,D3)
SUSPEND MODE COMPLIANCE
s PIN PROGRAMMABLE HIGH/LOW POWER
USB DEVICE REGISTRATION, WAKE-UP
CAPABILITY, USB DEVICE IDENTIFICATION
GENERAL
– USB hot plug and play interface.
– Control access and interrupt handling provided
through the USB interface.
– All FIFOS and FIFOS management needed in-
cluded for USB/ISDN data processing.
– Internal PLL to generate the USB 48MHz clock
from a 15.36MHz crystal.
– Internal regulator for 3.3V generation from USB
bus 5V.
– 48 pin TQFP package.
– 0.35 micron HCMOS 6 process.
DESCRIPTION
ST5481 combines ISDN link access and an USB
interface to allow a very simple USB/ISDN
modem design with all ISDN protocols and upper
applications processed into the HOST PC.
TQFP48
ORDERING NUMBER:
ST5481 TQF7
October 2000
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/18
1 page  
4 - SYNOPTIC
Figure 2 : Global Synoptic
ST5481
VREF-GEN
IREF
NRESET
S0
4
FLTPLL
15.36MHz
PLL
48MHz
15.36
CK48
VREF
TXCK_O
RXCK_O
S0 interface TXFS_O
RXFS_O
TXDATA
RXDATA
B1_W
STOP_OSC
MCLK
B2_W
D_W
NLSD
DEN
DREQ
I430
MACROCELL
NINT
SDO
SDI
SCK
NCS
TEST
B1, B2, D
FIFOS
for
isochonous
endpoints
CONTROL_DATA_OUT(7-0)
CONTROL_DATA_IN(7-0)
CHANNEL
ACCESS
and
FRAMING
Descriptor
ROM
256 bytes
USB Driver
4
USB Bus
Microwire
interface
Endpoint 1
controller
Endpoint 0
controller
TEST interface
Test pins
MODE(3-0)
USB
MACROCELL
CK48
CK12
TEST2-0
Power management and REGULATORS
RPSM 8 power pins
5/18
5 Page 
ST5481
USB Descriptors
During the USB request GET DESCRIPTOR, the device returns these values from an internal 256 byte
ROM.
Table 2 : Device Descriptor
ROM addr Offset
Field
Size Value
Description
08 0 bLengh
1 12h Size of this descriptor in bytes
09
1 bDescriptorType
1 01h Device Descriptor type
0A 2 bcdUSB
2 0101h USB spec release number 1.1
0C 4 bDeviceClass
1 FFh Vendor Specific Class code
0D
5 bDeviceSubClass
1 01h Vendor specific ISDN MODEM subclass
0E
6 bDeviceProtocol
1 01h Vendor specific ISDN SOFT MODEM control protocol
0F
7 bMaxPacketSize0
1 08h Max packet size for EP0
10 8 idVendor
2 0483h ST id vendor
12 10 idProduct
2 481xh Application id product 1
14 12 bcdDevice
2 01xxh Device release 2
16 14 iManufacturer
1 00h No specific manufacturer registred
17 15 iProduct
1 01h product id String descriptor index 1
18 16 iSerialNumber
1 00h No specific serial number registred
19
17 bNumConfigurations 1
01h Number of possible configurations
Notes 1. This word represents the hardware-software association. The value is programmable through 4 of the 16 bits. the lower bits values
are defined by pins ID3 to ID0.
2. This word represents the silicon hardware. The lower 8-bit value is defined at metal layer. The other 8 bits are written into the ROM
at diffusion layer.
Table 3 : Interface 0 as 0 Descriptor
ROM addr Offset
Field
Size Value
Description
20 0 bLengh
1 09h Size of this descriptor in bytes
21 1 bDescriptorType 1 02h Configuration Descriptor type
22 2 wTotalLengh
2 00CFh Total length of data byte returned for this configuration
24 4 bNumInterface
1 01h number of interfaces supported by this configuration
25 5 bConfigurationValue 1 01h value used to select this conf.
26 6 iConfiguration
1 00h No specific string descriptor for this configuration
27 7 bmAttributes
1 Self powered and remote wake-up abilities
XXh programmable 1
28 8 MaxPower
1 XXh max consumption programmable 1
Note 1. Theses words are defined by a transcoding of the pins CFG0, CFG1, RPSM : see power management section for coding of these
pins.
11/18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ST5481.PDF ] | |
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